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Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

2nd Edition

  • Manoj Sachdev
  • José Pineda de Gyvez

Part of the Frontiers in Electronic Testing book series (FRET, volume 34)

Table of contents

  1. Front Matter
    Pages I-XXI
  2. Manoj Sachdev, José Pineda de Gyvez
    Pages 1-22
  3. Manoj Sachdev, José Pineda de Gyvez
    Pages 23-67
  4. Manoj Sachdev, José Pineda de Gyvez
    Pages 69-110
  5. Manoj Sachdev, José Pineda de Gyvez
    Pages 111-150
  6. Manoj Sachdev, José Pineda de Gyvez
    Pages 151-223
  7. Manoj Sachdev, José Pineda de Gyvez
    Pages 225-287
  8. Manoj Sachdev, José Pineda de Gyvez
    Pages 289-315
  9. Manoj Sachdev, José Pineda de Gyvez
    Pages 317-324
  10. Back Matter
    Pages 325-328

About this book

Introduction

Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptable limits, new test methodologies and a deeper insight into the physics of defect-fault mappings are needed. In Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits state of the art of defect-oriented testing is presented from both a theoretical approach as well as from a practical point of view. Step-by-step handling of defect modeling, defect-oriented testing, yield modeling and its usage in common economics practices enables deeper understanding of concepts.

The progression developed in this book is essential to understand new test methodologies, algorithms and industrial practices. Without the insight into the physics of nano-metric technologies, it would be hard to develop system-level test strategies that yield a high IC fault coverage. Obviously, the work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.

Keywords

CMOS DSM DfM RAM SRAM VLSI defects integrated circuit logic testing yield

Editors and affiliations

  • Manoj Sachdev
    • 1
  • José Pineda de Gyvez
    • 2
  1. 1.University of WaterlooOntarioCanada
  2. 2.Philips Research LaboratoriesEindhoven University of TechnologyEindhovenThe Netherlands

Bibliographic information

  • DOI https://doi.org/10.1007/0-387-46547-2
  • Copyright Information Springer 2007
  • Publisher Name Springer, Boston, MA
  • eBook Packages Engineering
  • Print ISBN 978-0-387-46546-3
  • Online ISBN 978-0-387-46547-0
  • Series Print ISSN 0929-1296
  • Buy this book on publisher's site
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