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References
A. Allan and J.A. Walton, “Hierarchical critical area extraction with the EYE tools, ” Proc. 1995 IEEE Int. Workshop Defect and Fault Tolerance in VLSI Systems, pp. 28-36, Nov. 1995.
I. Chen and A.J. Strojwas, “RYE: A realistic yield simulator for structural faults,” Proc. International Test Conference 1987, Washington, DC, USA, 1-3 Sept. 1987, pp.31-42.
D.L. Critchow, R.H. Dennard, S. Schuster and E.Y. Rocher, “Design of Insulated-Gate Field-Effect Transistors and Large Scale Integrated Circuits for Memory and Logic Applications,” IBM Research Report RC 2290, Oct. 1968.
J.A. Cunningham, “The use and evaluation of yield models in integrated manufacturing,” IEEE Trans. On Semiconductor Manufacturing., vol. 3, pp. 60-71, May 1990.
A. V. Ferris-Prabhu, “Role of defect size distribution in yield modeling,” IEEE-Transactions on Electron Devices, vol.ED-32, no.9, p.1727-36, Sept. 1985.
A.V. Ferris Prabhu, “Modeling the critical areas in yield forecasts,” IEEE J. Solid State Circuits, vol. SC-20, no. 4, pp. 874-878, 1985.
A.V. Ferris Prabhu et. al. “Radial Yield variations in semiconductor wafers,” IEEE Circuits and Devices Magazine, vol.3, no. 2., pp. 42-47, 1987.
A. Gupta, W.A. Porter and J.W. Lathrop, “Defect analysis and yield degradation of integrated circuits,” IEEE J. Solid State circuits, vol. SC-9, no. 3, pp. 96-103, 1974.
I. Koren, Z. Koren, and C.H. Stapper, “A unified negative binomial distribution for yield analysis of defect tolerant circuits,” IEEE Trans. on Computers, vol. 42, pp. 724-737, June 1993.
I. Koren, Z. Koren, “Defect tolerance in VLSI circuits: Techniques and yield analysis,” Proc. IEEE, vol. 86, no. 9, pp. 1817- 1836, Sept. 1998.
W. Maly, “Computer Aided Design for VLSI circuit manufacturability,” Proc. IEEE, vol. 78, pp. 356-392, Feb. 1990.
H.G. Parks and E.A. Burke, “The nature of defect size distributions in semiconductor processes,” IEEE/SEMI Int. Sem. Manufct. Science Symp., pp. 131-135, 1989.
J.P. de Gyvez and D.K. Pradhan, Eds., IC Manufacturability: The Art of Process and Design Integration,” IEEE Press, 1999.
J.P. de Gyvez, “IC defect sensitivity for footprint type spot defects,” IEEE Trans. On Computer Aided Design, vol. 11, pp. 638-658, May 1992.
W. Maly, A.J. Strojwas and S.W. Director, “VLSI yield prediction and estimation: a unified framework,” IEEE Trans. on CAD, vol. CAD-5, no. 1, pp. 114-130, 1986.
W. Maly and J. Deszczka, “Yield estimation model for VLSI artwork evaluation, ” Electron. Lett., vol 19, no. 6, pp. 226-227, 1983.
W. Maly, “Yield models-comparative study,” Proc. of the International Workshop Defect and Fault Tolerance in VLSI Systems., vol.2, pp.15-32, Oct. 1989.
W. Maly, “Modeling of lithography related losses for CAD of VLSI circuits” IEEE Trans. On Computer Aided Design, vol. CAD-4, no. 3, pp. 166-177, 1985.
G.E. Moore, “What levels of LSI is best for you,” Electronics, vol. 43, pp.126-130, Feb. 16 1970.
B.T. Murphy, “Cost Size optima of monolithic integrated circuits,” Proc. IEEE, vol. 52, no. 12, pp. 1537-1545, 1964.
T. Okabe, M. Nagat, S. Shimada, “Analysis on yield of integrated circuits and a new expression for the yield,” Electron. Eng. Jpn., vol. 92, no. 6, pp. 135-141, 1972.
O. Paz and T.R. Lawson, “Modification of Poisson statistics: Modeling defects induced by diffusion,” IEEE J. Solid-State Circuits, vol. SSC-12, pp. 540-546, Oct. 1977.
R.B. Seeds, “Yield economic and logistic models for complex digital arrays,” IEEE Int. Conv. Rec., pt. 6, pp. 61-66, April 1967.
Z. Stamenkovic and N. Stojadinovic, “New defect size distribution function for estimation of chip critical area in integrated circuit yield models,” Electron. Lett., vol. 28, no. 6, pp. 528-530, Mar. 1992.
C.H. Stapper and R.J. Rosner, “Integrated circuit yield management and yield analysis: development and implementation,” IEEE Trans. On Semiconductor Manufacturing, vol. 8, no. 2, May 1995.
C.H. Stapper, “Yield Model for fault clusters within integrated circuits,” IBM J. Res. Dev. Vol. 28, no. 5, pp. 636-640, 1984.
C.H. Stapper, “On Yield, fault distributions and clustering of particles,” IBM J. Res. Dev., vol. 30, no. 3, pp. 326-338, 1986.
C.H. Stapper, F.M. Armstrong and K. Saji, “Integrated circuit yield statistics,” Proc. IEEE, vol. 71, pp. 453-470, Apr. 1983.
C.H. Stapper, “The effects of wafer to wafer defect density variations on integrated circuit defect and fault distirbutions, ” IBM J. Res. Dev., vol. 29, no. 1, pp. 87-97, 1985.
C.H. Stapper, “Modeling of integrated circuit sensitivities,” IBM J. Res. Dev., vol. 27, no. 6, pp. 549-557, 1983.
C.H. Stapper, “Fact and fiction in yield modeling,” Microelectronics Journal, vol. 20, nos. 1-2, pp. 129-151, 1989.
C.H. Stapper, “LSI yield modeling and process monitoring,” IBM J. Res. Develop., vol. 20, pp. 228-234, May 1976.
D.M.H. Walker, Yield Simulation for Integrated Circuits, Ph.D. Thesis, Carnegie Mellon University, CMU-CS-86143, pp. 138-139, July 1986.
T.J. Wallmark, “Design Considerations for integrated Electron Devices,” Proc. IRE, vol. 48, no. 3, pp. 293-300, 1960.
T. Yanagawa, “Yield degradation of integrated circuits due to spot defects,” IEEE Trans. On Electron. Devices, vol. ED-19, no. 2, pp. 190-197, 1972.
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Sachdev, M., Gyvez, J.P.d. (2007). Yield Engineering. In: Sachdev, M., Gyvez, J.P.d. (eds) Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits. Frontiers in Electronic Testing, vol 34. Springer, Boston, MA. https://doi.org/10.1007/0-387-46547-2_7
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