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Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits pp 69–110Cite as

Digital CMOS Fault Modeling

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Part of the book series: Frontiers in Electronic Testing ((FRET,volume 34))

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  1. University of Waterloo, Ontario, Canada

    Manoj Sachdev

  2. Philips Research Laboratories, Eindhoven University of Technology, Eindhoven, The Netherlands

    José Pineda de Gyvez

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    Manoj Sachdev

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    José Pineda de Gyvez

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Sachdev, M., Gyvez, J.P.d. (2007). Digital CMOS Fault Modeling. In: Sachdev, M., Gyvez, J.P.d. (eds) Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits. Frontiers in Electronic Testing, vol 34. Springer, Boston, MA. https://doi.org/10.1007/0-387-46547-2_3

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