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Defects in Logic Circuits and their Test Implications

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Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

Part of the book series: Frontiers in Electronic Testing ((FRET,volume 34))

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References

  1. R.C. Aitkens, “A Comparison of Defect Models for Fault Location with IDDQ Measurements,” Proceedings of International Test Conference, 1992, pp. 778-787.

    Google Scholar 

  2. P. Banerjee and J.A. Abraham, “Fault Characterization of VLSI Circuits,” Proceedings of IEEE International Conference on Circuits and Computers, September 1982, pp. 564-568.

    Google Scholar 

  3. P. Banerjee and J.A. Abraham, “Characterization and Testing of Physical Failures in MOS Logic Circuits,” IEEE Design & Test of Computers, vol. 1, pp. 76-86, August 1984.

    Article  Google Scholar 

  4. C.C. Beh, K.H. Arya, C.E. Radke and K.E. Torku, “Do Stuck Fault Models Reflect Manufacturing Defects?” Proceedings of International Test Conference, 1982, pp. 35-42.

    Google Scholar 

  5. D. Bhavsar, “A New Economical Implementation for Scannable Flip-Flops in MOS,” IEEE Design & Test, vol. 3, pp. 52-56, June 1986.

    Google Scholar 

  6. R. Bryant, “A Survey of Switch-Level Algorithms,” IEEE Design & Test of Computers, vol. 4, pp. 26-40, August 1987.

    Google Scholar 

  7. R. Chandramouli, “On Testing Stuck-Open Faults,” Proceedings of 13th Annual International Symposium on Fault Tolerant Computing Systems, June 1983, pp. 258-265.

    Google Scholar 

  8. K.W. Chiang and Z.G. Vranesic, “Test Generation For MOS Complex Gate Networks,” Proceedings of 12th Annual International Symposium on Fault Tolerant Computing Systems, June 1982, pp. 149-157.

    Google Scholar 

  9. E.B. Eichelberger and T.W. Williams, “A Logic Design Structure for LSI Testability,” Journal of Design Automation and Fault Tolerant Computing, vol. 2, no. 2, pp. 165-178, May 1978.

    Google Scholar 

  10. Y.M. El-Ziq and R.J. Cloutier, “Functional Level Test Generation for Stuck-Open Faults in CMOS VLSI,” Proceedings International Test Conference, 1981, pp. 536-546.

    Google Scholar 

  11. F.J. Ferguson and J.P. Shen, “Extraction and Simulation of Realistic CMOS Faults using Inductive Fault Analysis,” Proceedings of International Test Conference, 1988, pp. 475-484.

    Google Scholar 

  12. S. Funatsu, N. Wakatsuki and T. Arima, “Test Generation Systems in Japan,” Proceedings of 12th Design Automation Conference, 1975, pp. 114-122.

    Google Scholar 

  13. J. Galiay, Y. Crouzet and M. Vergniault, “Physical versus Logical Fault Models in MOS LSI Circuits: Impact on Their Testability,” IEEE Transaction on Computers, vol. C-29, no. 6, pp. 527-531, June 1980.

    Google Scholar 

  14. C.F. Hawkins and J.M. Soden, “Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICs,” Proceedings of International Test Conference, 1985, pp. 544-555.

    Google Scholar 

  15. C.F. Hawkins and J.M. Soden, “Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs,” Proceedings of International Test Conference, 1986, pp. 443-451.

    Google Scholar 

  16. C. F. Hawkins, J. M. Soden, A. Righter, and J. Ferguson, “Defect Classes - An Overdue Paradigm for CMOS IC Testing,” Proceedings of International Test Conference, 1994, pp. 413-425.

    Google Scholar 

  17. S.K. Jain and V.D. Agrawal, “Modeling and Test Generation Algorithm for MOS Circuits,” IEEE Transactions on Computers, vol. 34, no. 5, pp. 426-43, May 1985.

    Google Scholar 

  18. N.K. Jha and S. Kundu, Testing and Reliable Design of CMOS Circuits, Boston: Kluwer Academic Publishers, 1990.

    Google Scholar 

  19. Krishnaswamy V., Ma A.B., Vishakantaiah P., “A study of bridging defect probabilities on a Pentium (TM) 4 CPU,” IEEE Int. Test Conf., 2001, pp. 688–695.

    Google Scholar 

  20. B.Kaczer, R.Degraeve, E. Augendre, M. Jurczak, and G. Groeseneken, “Experimental verification of SRAM cell functionality after hard and soft gate oxide breakdowns,” European Solid-State Device Research Conf. (ESSDERC), pp. 75-78, 2003.

    Google Scholar 

  21. B. Kruseman, R. van Veen, K. van Kaam, “The Future of delta IDDQ testing,” in Proc. of ITC, pp. 101-110, 2001.

    Google Scholar 

  22. K.J. Lee and M.A. Breuer, “Design and Test Rules for CMOS Circuits to Facilitate IDDQ Testing of Bridging Faults,” IEEE Transactions on Computer-Aided Design, vol. 11, no.5, pp. 659-669, May 1992.

    Article  Google Scholar 

  23. W. Maly, F.J. Ferguson and J.P. Shen, “Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells,” Proceedings of International Test Conference, 1984, 390-399.

    Google Scholar 

  24. P. C. Maxwell, R. C. Aitken, V. Johansen and I. Chiang, “The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need?,” Proceedings of International Test Conference, 1992, pp. 168-177.

    Google Scholar 

  25. M.R. Mercer, and V.D. Agrawal, “A Novel Clocking Technique for VLSI Circuits Testability,” IEEE Journal of Solid State Circuits, vol. sc-19, no. 2, pp. 207-212, April 1984.

    Google Scholar 

  26. C. Metra, M. Favalli, P. Olivo, and B. Ricco, “Testing of Resistive Bridging Faults in CMOS Flip-Flop,” Proceedings of European Test Conference, 1993, pp. 530- 531.

    Google Scholar 

  27. Metra C., Di Francescantonio S., Mak TM., “Implications of Clock Distribution Faults and Issues with Screening them during Manufacturing Testing,” IEEE Trans. on Computers, Vol. 53, No. 5, pp. 531-546, 2004.

    Article  Google Scholar 

  28. F. Monsieur, E. Vincent, D. Roy, S. Bruyere, G. Pananakakis, and G. Ghibaudo, “Time to breakdown and voltage to breakdown modeling for ultra-thin oxides (Tox 32 Å),” in Proc. IEEE Int. Reliability Workshop, 2001, pp. 20–25.

    Google Scholar 

  29. K. Okada, H. Kubo, A. Ishinaga, and K. Yoneda, “A concept of gate oxide lifetime limited by “B-mode” stress induced leakage currents in direct tunneling regime,” Symp. VLSI Technol. Dig., pp. 57-58, 1999.

    Google Scholar 

  30. R. Perry, “IDDQ Testing in CMOS Digital ASIC’s - Putting It All Together,” Proceedings of IEEE International Test Conference, 1992, pp. 151-157.

    Google Scholar 

  31. F. Peters and S. Oostdijk, “Realistic Defect Coverages of Voltage and Current Tests,” Proc. of IEEE International Workshop on IDDQ Testing, 1996, pp. 4-8.

    Google Scholar 

  32. T. Pompl, H. Wurzer, M. Kerber, R.C.W. Wilkins, I. Eisele, “Influence of soft breakdown on NMOSFET device characteristics”, Proc. IRPS, pp. 82-87, 1999.

    Google Scholar 

  33. A. Platts and D. Taylor, “Rapid Inductive Fault Analysis for High-Yield Circuits,” Microelectronics Journal, vol. 33, No. 3, p 279-284, 2002.

    Article  Google Scholar 

  34. R. Rodriguez-Montanes, J. Figueras and R. Rubio, “Current vs. Logic Testability of Bridges in Scan Chains,” Proceedings of European Test Conference, 1993, pp. 392-396.

    Google Scholar 

  35. M. Sachdev, “Transforming Sequential Logic for Voltage and IDDQ Testing,” Proceedings of European Design and Test Conference, 1994, pp. 361-365.

    Google Scholar 

  36. M. Sachdev, “Testting Defects in Scan Chains,” IEEE Design & Test of Computers, vol. 12, pp. 45-51, December 1995.

    Article  Google Scholar 

  37. M. Sachdev, “IDDQ and Voltage Testable CMOS Flip-flop Configurations,” Proceedings of International Test Conference, 1995, pp. 534-543.

    Google Scholar 

  38. K. F. Schuegraf and C. Hu, “Reliability of thin SiO2,” Proceedings of IEE, vol. 9, pp. 989-1004, September 1994.

    Google Scholar 

  39. J. Segura, C. Benito, A Rubio and C.F. Hawkins, “A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level,” Proceedings of International Test Conference, 1995, pp. 544-551.

    Google Scholar 

  40. O. Semenov, A. Vassighi and M. Sachdev, “Leakage current in sub-quarter micron MOSFET: A perspective on stressed delta IDDQ testing,” Journal of Electronic Testing (JETTA), vol. 19, No.3, pp. 341-352, 2003.

    Article  Google Scholar 

  41. S. Sengupta, S. Kundu, S. Chakravarty, P. Parvathala, R. Galivanche, G. Kosonocky, M. Rodgers, TM. Mak, “Defect-Based Test: A Key Enabler for Successful Migration to Structural Test,” Intel Tech. Journal, Q1, pp 1-14, 1999. http://developer.intel.com/technology/itj/q11999/pdf/defect_based.pdf

    Google Scholar 

  42. J.P. Shen, W. Maly and F.J. Ferguson, “Inductive Fault Analysis of MOS Integrated Circuits,” IEEE Design & Test of Computers, vol. 2, pp. 13-26, December 1985.

    Google Scholar 

  43. J. M. Soden and C.F. Hawkins, “Test Considerations for Gate Oxide Shorts in CMOS ICs,” IEEE Design & Test of Computers, vol. 3, pp. 56-64, August 1986.

    Article  Google Scholar 

  44. T. Storey, W. Maly, J. Andrews, and M. Miske, “Stuck Fault and Current Testing Comparison Using CMOS Chip Test,” Proceedings of International Test Conference, 1991, pp. 311-318.

    Google Scholar 

  45. J.H. Suehle, “Ultra thin gate oxide reliability: physical models, statistics, and characterization,” IEEE Trans. Electron Devices, vol. 49, pp. 958-971, June 2002.

    Article  Google Scholar 

  46. M. Syrzycki, “Modeling of Gate Oxide Shorts in MOS Transistors,” IEEE Transactions on Computer Aided Design, vol. 8, no. 3, pp. 193-202, March 1989.

    Article  Google Scholar 

  47. H.T. Vierhaus, W. Meyer, and U. Glaser, “CMOS Bridges and Resistive Faults: IDDQ versus Delay Effects,” Proceedings of International Test Conference, 1993, pp. 83-91.

    Google Scholar 

  48. R.L. Wadsack, “Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits,” Bell Systems Technical Journal, vol. 57, no.5, pp. 1449-1474, May-June 1978.

    Google Scholar 

  49. T.W. Williams and K.P. Parker, “Design for Testability–A Survey,” Proceedings of the IEEE, vol. 71, no. 1, pp. 98-113, January 1983.

    Google Scholar 

  50. S. T. Zacariah and S. Chakarvarty, “A Scalable and Efficient Methodology to Extract Two Node Bridges from Large Industrial Circuits,” Proceedings of IEEE International Test Conference, pp. 750-759, November 2000.

    Google Scholar 

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Author information

Authors and Affiliations

  1. University of Waterloo, Ontario, Canada

    Manoj Sachdev

  2. Philips Research Laboratories, Eindhoven University of Technology, Eindhoven, The Netherlands

    José Pineda de Gyvez

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  1. Manoj Sachdev
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  2. José Pineda de Gyvez
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Editors and Affiliations

  1. University of Waterloo, Ontario, Canada

    Manoj Sachdev

  2. Philips Research Laboratories, Eindhoven University of Technology, Eindhoven, The Netherlands

    José Pineda de Gyvez

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Sachdev, M., Gyvez, J.P.d. (2007). Defects in Logic Circuits and their Test Implications. In: Sachdev, M., Gyvez, J.P.d. (eds) Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits. Frontiers in Electronic Testing, vol 34. Springer, Boston, MA. https://doi.org/10.1007/0-387-46547-2_4

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  • DOI: https://doi.org/10.1007/0-387-46547-2_4

  • Publisher Name: Springer, Boston, MA

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