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References
M. Abadir, and A.P. Ambler, Economics of Electronic Design, Manufacture and Test, Boston: Kluwer Academic Publishers, 1994.
V.D. Agrawal, S.C. Seth, and P. Agrawal, “Fault Coverage Requirement in Production Testing of LSI Circuits”, IEEE Journal of Solid State Circuits, vol. SC-17, no.1, pp. 57–61, February 1982.
A.P. Ambler, M. Abadir, and S. Sastry, Economics of Design and Test for Electronic Circuits and Systems, New York: Ellis Horwood, 1992.
K. Baker, “QTAG: A Standard for Test Fixture Based IDDQ/ISSQ Monitors,” Proceedings of the IEEE International Test Conference, pp. 194–202, 1992.
G. Baccarani, M.R. Wordeman, and R.H. Dennard, “Generalized Scaling Theory and its Application to a \raise.5ex\scriptstyle 1\kern-.1em/ \kern-.15em\lower.25ex\hboxriptstyle 4 micrometer MOSFET design,” IEEE Transactions on Electron Devices, vol. ED-31, pp. 452–462, Apr. 1984.
J. Bardeen, and W. Brattain, “The Transistor, a Semiconductor Triode,” Phys. Rev., vol. 74, pp. 230, Jul. 1948.
S.D. Brown, Field-Programmable Devices: Technology, Applications, Tools, 2nd Edition, Los Gatos: Stan Baker Associates, 1995.
C. Dislis, J.H. Dick, I.D. Dear, and A.P. Ambler, Test Economics and Design For Testability, New York: Ellis Horward, 1995.
D.L. Crook, “Evolution of VLSI Reliability Engineering,” Proceedings of the IEEE International Reliability Physics Symposium, pp. 2–11, 1990.
R. H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rideout, E. Bassous, and A.R. Leblanc, “Design of ion-implanted MOSFETs with very small physical dimensions,” IEEE Journal of Solid State Circuits, vol. SC-9, pp. 256–268, Oct. 1974.
F.J. Ferguson, and J.P. Shen, “Extraction and Simulation of Realistic CMOS Faults using Inductive Fault Analysis,” Proceedings of the IEEE International Test Conference, pp. 475–484, 1988.
A.V. Ferris-Prabhu, “Computation of the critical area in semiconductor yield theory,” Proceedings of the European Conference on Electronic Design Automation, pp.171–173, 1984.
D.J. Frank, R.H. Dennard, E. Nowak, P.M. Solomon, Y. Taur, and H.P. Wong, “Device Scaling Limits of Si MOSFET and Their Application Dependencies,” Proceedings of the IEEE, vol. 89, no. 3, Mar. 2001.
C. Hawkins, and J. Soden, “Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs,” Proceedings of the IEEE International Test Conference, pp. 443–451, 1986.
E.R. Hnatek, “IC Quality - Where Are We?” Proceedings of the IEEE International Test Conference, pp. 430–445, 1987.
E.R. Hnatek, Integrated Circuits Quality and Reliability – 2nd Edition, New York: Marcel Dekker, Inc., 1995.
R. Gayle, “The Cost of Quality: Reducing ASIC Defects with IDDQ, At-Speed Testing and Increased Fault Coverage,” Proceedings of the IEEE International Test Conference, pp. 285–292, 1993.
J. Geerlings, E. Desmicht, and H. de Perthuis, “A single-chip MPEG2 CODEC for DVD+RW”, IEEE International Solid-State Circuits Conference, vol. 1, pp. 40–41, 2003.
R. Gulati, and C. Hawkins, IDDQ Testing of VLSI Circuits, Boston: Kluwer Academic Publishers, 1993.
O. Heil, “Improvements in or relating to electrical amplifiers and other control arrangements and devices”, British Patent no. 439,457, 1935.
C. Hora, R. Segers, S. Eichenberger, M. Lousberg, “An effective Diagnosis Method to Support Yield Improvement,” Int. Test Conference, pp. 260–269, Oct. 2002
International Technology Roadmap for Semiconductors [Online], Available: http://public.itrs.net.
M. Inoue, T. Yamada, and A. Fujiwara, “A New Testing Acceleration Chip for Low-Cost Memory Test,” IEEE Design and Test of Computers, vol. 10, pp. 15–19, Mar. 1993.
J. Khare, and W. Maly, From Contamination to Defects, Faults and Yield Loss, Boston: Kluwer Academic Publishers, 1996.
J. Kilby, “Semiconductor Device-and-Lead Structure,” U.S. Patent no. 2,981,877, 1959.
J. P. M. van Lammeren, “ICCQ: A Test Method for Analogue VLSI Based on Current Monitoring,” IEEE International Workshop on IDDQ Testing, pp. 24–28, 1997.
J. E. Lilenfeld, “Method and apparatus for controlling electric currents”, U.S. Patent no. 1,745,175, 1926.
P. Maxwell, P. O’Neill, R. Aitken, R. Dudley, N. Jaarsma, M. Quach, D. Wiseman, “Current ratios: a self-scaling technique for production IDDQ testing,” Proceedings of the IEEE International Test Conference, pp. 1148–1156, 2000.
P. Mazumder, and K. Chakraborty, Testing and Testable Design of High-Density Random-Access Memories, Boston: Kluwer Academic Publishers, 1996.
S. D. McEuen, “IDDQ Benefits,” Proceedings of the IEEE VLSI Test Symposium, pp. 285–290, 1991.
E.J. McCluskey, and F. Buelow, “IC Quality and Test Transparency,” Proceedings of the IEEE International Test Conference, pp. 295–301, 1988.
A. C. Miller, “IDDQ Testing in Deep Submicron Integrated Circuits,” Proceedings of the IEEE International Test Conference, pp. 724–729, 1999.
G. Moore, “Cramming More Components into Integrated Circuits,” Electronics, vol. 38, no. 8, Apr. 1965.
B. Mustafa Pulat, and L. M. Streb, “Position of Component Testing in Total Quality Management (TQM),” Proceedings of the IEEE International Test Conference, pp. 362–366, 1992.
R. Perry, “IDDQ testing in CMOS digital ASICs,” Journal of Electronic Testing: Theory and Applications, vol. 3, pp. 317–325, Nov. 1992.
J. Rajski, “DFT technology for low cost IC manufacture test”, Electronic Engineering Design, pp. 21, Jun. 2002.
M. Rencher, “Yields can be improved via design techniques”, EE Times special publication: “What’s Yield Got To Do With IC Design?,” 2003.
J. Roberts, and S. Burke, “Intel to take 475M charge to cover costs in Pentium recall”, Computer Reseller News, iss. 614, pp. 135, Jan. 1995.
M. Sachdev, “A Defect Oriented Testability Methodology for Analog Circuits,” Journal of Electronic Testing: Theory and Applications, vol. 6, no. 3, pp. 265–276, Jun. 1995.
M. Sachdev, “Reducing the CMOS RAM Test Complexity with IDDQ and Voltage Testing,” Journal of Electronic Testing: Theory and Applications, vol. 6, no. 2, pp. 191–202, Apr. 1995.
M. Sachdev, “Deep Sub-micron IDDQ Testing: Issues and Solutions,” Proceedings of the European Design and Test Conference, pp. 271–278, 1997.
M. Sachdev, P. Janssen, and V. Zieren, “Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs,” Proceedings of the IEEE International Test Conference, pp. 204–213, 1998.
M. Sachdev, “Current-Based Testing for Deep-Submicron VLSI”, IEEE Design and Test of Computers, pp. 77–84, Mar. 2001.
A. Schafft, D. A. Baglee, and P. E. Kennedy, “Building-in Reliability: Making it Work,” Proceedings of the IEEE International Reliability Physics Symposium, pp. 1–7, 1991.
W. Schockley, “The Theory of pn-junction in Semiconductors and pn-junction Transistors,” BSTJ, vol. 28, p. 435, 1949.
O. Semenov, A. Vassighi, M. Sachdev, A. Keshavarzi, and C. F. Hawkins, “Effect of CMOS technology scaling on thermal management during burn-in”, IEEE Transactions on Semiconductor Manufacturing, vol. 16, iss. 4, pp. 686–695, Nov. 2003.
S.C. Seth, and V.D. Agrawal, “Characterizing the LSI Yield Equation from Wafer Test Data,” IEEE Transactions on Computer-Aided Design, vol. CAD-3, no. 2, pp. 123–126, Apr. 1984.
J.M. Soden, C.F. Hawkins, R.K. Gulati, and W. Mao, “IDDQ Testing: A Review,” Journal of Electronic Testing: Theory and Applications, vol. 3, pp. 291–303, Nov. 1992.
M. Syrzycki, “Modeling of Spot Defects in MOS Transistors,” Proceedings of the IEEE International Test Conference, pp. 148–157, 1987.
E. Takeda et al., “VLSI Reliability Challenges: From Device Physics to Wafer Scale Systems,” Proceedings of the IEEE, vol. 81, no.5, pp. 653–674, May 1993.
“Test and Test Equipment”, 2003 International Technology Roadmap for Semiconductors [Online], Available: http://public.itrs.net/Files/2003ITRS/ Test2003.pdf.
F. Wanlass, “Low Stand-By Power Complementary Field Effect Circuit,” U.S. Patent no. 3,356,858, 1963.
F. Wanlass, and C. Sah, “Nanowatt Logic Using Field-Effect Metal-Oxide Semiconductor Triodes,” ISSCC Digest of Technical Papers, pp. 32–33, February 1963.
P. Wiscombe, “A Comparison of Stuck-At Fault Coverage and IDDQ Testing on Defect Levels,” Proceedings of the IEEE International Test Conference, pp. 293–299, 1993.
T. W. Williams, R. H. Dennard, and R. Kapur, “Iddq Analysis: Sensitivity Analysis of Scaling,” Proceedings of the IEEE International Test Conference, pp. 786–792, 1996.
T. W. Williams, R. Kapur, and M. R. Mercer, “Iddq Testing for High Performance CMOS – The Next Ten Years,” Proceedings of the European Design and Test Conference, pp. 578–583, 1996.
P. Varma, A.P. Ambler, and K. Baker, “An Analysis of the Economics of Self- Test,” Proceedings of the IEEE International Test Conference, pp. 20–30, 1984.
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Sachdev, M., Gyvez, J.P.d. (2007). Introduction. In: Sachdev, M., Gyvez, J.P.d. (eds) Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits. Frontiers in Electronic Testing, vol 34. Springer, Boston, MA. https://doi.org/10.1007/0-387-46547-2_1
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