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Cache and Interconnect Architectures in Multiprocessors

  • Book
  • © 1990

Overview

Editors:
  1. Michel Dubois

    1. University of Southern California, USA

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  2. Shreekant S. Thakkar

    1. Sequent Computer Systems, USA

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Table of contents (14 chapters)

  1. Front Matter

    Pages i-xiii
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  2. TLB Consistency and Virtual Caches

    1. The Cost of TLB Consistency

      • Patricia J. Teller
      Pages 1-14

    2. Virtual-Address Caches in Multiprocessors

      • Michel Cekleov, Michel Dubois, Jin-Chin Wang, Fayé A. Briggs
      Pages 15-35

  3. Simulation and Performance Studies — Cache Coherence

    1. A Critique of Trace-Driven Simulation for Shared-Memory Multiprocessors

      • Philip Bitar
      Pages 37-52

    2. Performance of Symmetry Multiprocessor System

      • Shreekant S. Thakkar
      Pages 53-82

    3. Analysis of Cache Invalidation Patterns in Shared-Memory Multiprocessors

      • Anoop Gupta, Wolf-Dietrich Weber
      Pages 83-107

    4. Memory-Access Penalties in Write-Invalidate Cache Coherence Protocols

      • Jin-Chin Wang, Michel Dubois
      Pages 109-130

    5. Performance of Parallel Loops using Alternative Cache Consistency Protocols on a Non-Bus Multiprocessor

      • Russell M. Clapp, Trevor N. Mudge, James E. Smith
      Pages 131-152

    6. Predicting the Performance of Shared Multiprocessor Caches

      • Hendrik A. Goosen, David R. Cheriton
      Pages 153-164

  4. Cache Coherence Protocols

    1. The Cache Coherence Protocol of the Data Diffusion Machine

      • Erik Hagersten, Seif Haridi, David H. D. Warren
      Pages 165-188

    2. SCI (Scalable Coherent Interface) Cache Coherence

      • David V. James
      Pages 189-208

  5. Interconnect Architectures

    1. Performance Evaluation of Wide Shared Bus Multiprocessors

      • Andy Hopper, Alan Jones, Dimitris Lioupis
      Pages 209-222

    2. Crossbar-Multi-Processor Architecture

      • Vason P. Srini
      Pages 223-243

    3. “CHESS” Multiprocessor A Processor-Memory Grid for Parallel Programming

      • Dimitris Lioupis, Nikos Kanellopoulos
      Pages 245-257

  6. Software Cache Coherence Schemes

    1. Software-directed Cache Management in Multiprocessors

      • Hoichi Cheong, Alexander V. Veidenbaum
      Pages 259-276

  7. Back Matter

    Pages 277-277
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Keywords

About this book

Cache And Interconnect Architectures In Multiprocessors Eilat, Israel May 25-261989 Michel Dubois UniversityofSouthernCalifornia Shreekant S. Thakkar SequentComputerSystems The aim of the workshop was to bring together researchers working on cache coherence protocols for shared-memory multiprocessors with various interconnect architectures. Shared-memory multiprocessors have become viable systems for many applications. Bus­ based shared-memory systems (Eg. Sequent's Symmetry, Encore's Multimax) are currently limited to 32 processors. The fIrst goal of the workshop was to learn about the performance ofapplications on current cache-based systems. The second goal was to learn about new network architectures and protocols for future scalable systems. These protocols and interconnects would allow shared-memory architectures to scale beyond current imitations. The workshop had 20 speakers who talked about their current research. The discussions were lively and cordial enough to keep the participants away from the wonderful sand and sun for two days. The participants got to know each other well and were able to share their thoughts in an informal manner. The workshop was organized into several sessions. The summary of each session is described below. This book presents revisions of some of the papers presented at the workshop.

Editors and Affiliations

  • University of Southern California, USA

    Michel Dubois

  • Sequent Computer Systems, USA

    Shreekant S. Thakkar

Bibliographic Information

  • Book Title: Cache and Interconnect Architectures in Multiprocessors

  • Editors: Michel Dubois, Shreekant S. Thakkar

  • DOI: https://doi.org/10.1007/978-1-4613-1537-7

  • Publisher: Springer New York, NY

  • eBook Packages: Springer Book Archive

  • Copyright Information: Kluwer Academic Publishers 1990

  • Hardcover ISBN: 978-0-7923-9074-9Published: 31 July 1990

  • Softcover ISBN: 978-1-4612-8824-4Published: 19 September 2011

  • eBook ISBN: 978-1-4613-1537-7Published: 06 December 2012

  • Edition Number: 1

  • Number of Pages: XIV, 277

  • Topics: Processor Architectures

  • Industry Sectors: IT & Software

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