Abstract
Trace-driven simulation of a multiprocessor system faces serious validity issues since multiprocessor trace-driven simulation generally cannot represent interacting processes correctly the interactions represented by multiprocessor trace-driven simulation generally do not correspond to correct execution of the algorithm in the hypothetical architecture. Consequently, multiprocessor trace-driven simulation must generally be validated by other modeling/simulation techniques. Low-level modeling/simulation provides low-level accuracy, while high-level modeling/simulation provides high-level insight and the ability to generalize.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Bibliography
Archibald, J., Baer, J-L. 1986. “An evaluation of cache coherence solutions in shared-bus multiprocessors” ACM Trans, on Computer Systems, 4(4), Nov. 1986, 273–298.
Bitar, P., Despain, A.M. 1986. “Multiprocessor cache synchronization: issues, innovations, evolution” 13th ISCA, 1986, 424–433.
Dubois, M., Briggs, F.A. 1982. “Effects of cache coherency in multiprocessors.” IEEE Trans. Computers, C-31(11), Nov. 1982, 1083–01099.
Dubois, M., Wang, J-C. 1988. “Shared data contention in a cache coherence protocol.” 14th ICPP, August 1988, 146–155.
Eggers, S.J. 1989. “Simulation analysis of data sharing in shared memory multiprocessors,” March 1989, Ph.D. dissertation, Tech. Report UCB/CSD 89/501, Computer Science Division, U. of Calif., Berkeley, CA 94720.
Eggers, S.J., Katz, R.H. 1988. “A characterization of sharing in parallel programs and its application to coherency protocol evaluation,” 15th ISCA, 1988, 373–383.
Eggers, S.J., Katz, R.H. 1989a. “The effect of sharing on the cache and bus performance of parallel programs,” 3rd ASPLOS, 1989, 257–0270.
Eggers, S.J., Katz, R.H. 1989b. “Evaluating the performance of four0 snooping cache coherency protocols,” 16th ISCA, 1989, 2–15.
Thompson, J.G. 1987. “Efficient analysis of caching systems,” Oct. 1987, Ph.D. dissertation, Tech. Report UCB/CSD 87/374, Computer Science Division, U. of Calif., Berkeley, CA 94720.
Thompson, J.G., Smith, A.J. 1989. “Efficient (stack) algorithms for analysis of write-back and sector memories,” ACM Trans, on Computer Systems, 7(1), February 1989, 78–117.
Vernon, M.K., Holliday, M.A. 1986. “Performance analysis of multiprocessor cache consistency protocols using generalized timed petri nets.” ACM SIGMETRICS, 1986.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1990 Kluwer Academic Publishers
About this chapter
Cite this chapter
Bitar, P. (1990). A Critique of Trace-Driven Simulation for Shared-Memory Multiprocessors. In: Dubois, M., Thakkar, S.S. (eds) Cache and Interconnect Architectures in Multiprocessors. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1537-7_3
Download citation
DOI: https://doi.org/10.1007/978-1-4613-1537-7_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-8824-4
Online ISBN: 978-1-4613-1537-7
eBook Packages: Springer Book Archive