Abstract
Most general-purpose computers support virtual memory. Generally, the cache associated with each processor is accessed with a physical address obtained after translation of the virtual address in a Translation Lookaside Buffer (TLB). Since today’s uniprocessors are very fast, it becomes increasingly difficult to include the TLB in the cache access path and still avoid wait states in the processor. The alternative is to access the cache with virtual addresses and to access the TLB on misses only. This configuration reduces the average memory access time, but it is a source of consistency problems which must be solved in hardware or software. The basic causes of these problems are the demapping and remapping of virtual addresses, the presence of synonyms, and the maintenance of protection and statistical bits. Some of these problems are addressed in this paper and solutions are compared.
This paper is a condensed version of a technical report [3].
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Bibliography
Maurice J. Bach. The design of the UNIX operating system. Prentice-Hall, 1986.
Ray Cheng. Virtual address cache in UNIX. Proc. 1987 summer usenix conference, pages 217–224, 1987.
Michel Cekleov, Michel Dubois, Jin-Chin Wang and Faye’ A. Briggs, Virtual-Address Caches, U.S.C. Technical Report No. CENG 89–701.
Craig R. Frink and Paul J. Roy. The cache architecture of the Apollo DN4000. Proc. 1988 Compcon, IEEE, pages 300–302, 1988.
Borivoje Furht and Veljko Milutinovic. A survey of microprocessor architectures for memory management. Computer, pages 48–67, Mar., 1987.
James R. Goodman. Coherency for multiprocessor virtual address caches. Proc. 2nd International Conference on Architecture Support For Programming Languages and Operating Systems, ACM, 1987.
David A. Patterson. Reduced instruction set computer. Communications of the ACM. 28, 1, pages 8–21, Jan., 1985.
Alan J. Smith. Cache memories. ACM Computing Surveys, 14, 3, pages 473–530, Sept., 1982.
Paul Sweazey and Alan J. Smith. A class of compatible cache consistency protocols and their support by the IEEE Futurebus. Proc. of the 13th Annual International Synmposium on Computer Architecture, pages 414–423, June, 1986.
William Van Loo. Maximize performance by choosing best memory. Computer Design, pages 89–94, Aug., 1987.
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© 1990 Kluwer Academic Publishers
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Cekleov, M., Dubois, M., Wang, JC., Briggs, F.A. (1990). Virtual-Address Caches in Multiprocessors. In: Dubois, M., Thakkar, S.S. (eds) Cache and Interconnect Architectures in Multiprocessors. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1537-7_2
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DOI: https://doi.org/10.1007/978-1-4613-1537-7_2
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