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Virtual-Address Caches in Multiprocessors

  • Michel Cekleov
  • Michel Dubois
  • Jin-Chin Wang
  • Fayé A. Briggs

Abstract

Most general-purpose computers support virtual memory. Generally, the cache associated with each processor is accessed with a physical address obtained after translation of the virtual address in a Translation Lookaside Buffer (TLB). Since today’s uniprocessors are very fast, it becomes increasingly difficult to include the TLB in the cache access path and still avoid wait states in the processor. The alternative is to access the cache with virtual addresses and to access the TLB on misses only. This configuration reduces the average memory access time, but it is a source of consistency problems which must be solved in hardware or software. The basic causes of these problems are the demapping and remapping of virtual addresses, the presence of synonyms, and the maintenance of protection and statistical bits. Some of these problems are addressed in this paper and solutions are compared.

Keywords

Physical Address Page Table Virtual Address Translation Lookaside BufJer Occupancy Ratio 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Kluwer Academic Publishers 1990

Authors and Affiliations

  • Michel Cekleov
    • 1
  • Michel Dubois
    • 2
  • Jin-Chin Wang
    • 2
  • Fayé A. Briggs
    • 1
  1. 1.Advanced Development DivisionSun Microsystems Inc.Mountain View CaliforniaUSA
  2. 2.Department of Electrical Engineering SystemsUniversity of Southern CaliforniaLos AngelesUSA

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