Abstract
In this paper we describe the architecture of a parallel computer named “CHESS” designed for the parallel execution of imperative languages. It features a grid of processors and memories which connect with each other to form a processing surface onto which a program is mapped. The grid can be implemented using standard bus technology and 4N caches. A diffusion algorithm distributes the work load and minimizes long haul communications between processors. The resulting computer architecture provides a uniform picture to the user and a familiar programming model with increased performance.
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© 1990 Kluwer Academic Publishers
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Lioupis, D., Kanellopoulos, N. (1990). “CHESS” Multiprocessor A Processor-Memory Grid for Parallel Programming. In: Dubois, M., Thakkar, S.S. (eds) Cache and Interconnect Architectures in Multiprocessors. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1537-7_13
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DOI: https://doi.org/10.1007/978-1-4613-1537-7_13
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-8824-4
Online ISBN: 978-1-4613-1537-7
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