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Practical Formal Methods for Hardware Design

  • Book
  • © 1997

Overview

Editors:
  1. Carlos Delgado Kloos

    1. Depto. Ingeniería, Universidad Carlos III de Madrid, Leganés/Madrid, Spain

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  2. Werner Damm

    1. Fachbereich Informatik, Abt. Rechnerarchitektur, Universität Oldenburg, Oldenburg, Germany

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    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Research Reports Esprit (ESPRIT)

Part of the book sub series: Project 6128.FORMAT (3477)

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Table of contents (13 chapters)

  1. Front Matter

    Pages I-XIV
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  2. Introduction

    1. Introduction

      • Carlos Delgado Kloos, Werner Damm, Juan Goicolea
      Pages 1-4

  3. Overview

    1. Front Matter

      Pages 5-5
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    2. Design Methodology for Complex VLSI Devices

      • Massimo Bombana, Fabrizio Ferrandi
      Pages 7-22

    3. Specification Languages

      • Werner Damm, Gert Döhmen, Johannes Helbig, Peter Kelb, Rainer Schlör, Werner Grass et al.
      Pages 23-51

    4. Verification Flow

      • Werner Damm, Gert Döhmen, Ronald Herrmann, Peter Kelb, Hergen Pargmann, Rainer Schlör
      Pages 52-80

    5. Synthesis Flow

      • Werner Grass, Wolf-Dieter Tiedemann, Carlos Delgado Kloos, André Marin López
      Pages 81-96

  4. Industrial Experience

    1. Front Matter

      Pages 97-97
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    2. Application of a Formal Verification Toolset to the Design of Integrated Circuits in an Industrial Environment

      • Pierre Plaza, José Luis Conesa, Fernando Palao
      Pages 99-131

    3. Italtel Application of the FORMAT Design Flow

      • Massimo Bombana, Patrizia Cavalloro, Fabrizio Ferrandi, Fernanda Salice
      Pages 132-158

    4. Siemens Industrial Experience

      • Ronald Herrmann, Jörg Bormann, Thomas Filkorn, Jörg Lohse, Hans-Albert Schneider
      Pages 159-172

  5. Technical Background

    1. Front Matter

      Pages 173-173
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    2. The FORMAT Model Checker

      • Andreas Scholz, Thomas Filkorn, Jörg Lohse, Hans-Albert Schneider, Erik Tidén, Peter Warkentin
      Pages 175-183

    3. Reasoning

      • Nick Chapman, Simon Finn, Michael P. Fourman
      Pages 184-216

    4. VHDL Formal Modeling and Analysis

      • Luis Entrena, Serafín Olcoz, Juan Goicolea
      Pages 217-228

    5. Synthesis Techniques

      • Wolf-Dieter Tiedemann, Stefan Lenk, Christian Grobe, Werner Grass, Carlos Delgado Kloos, Andrés Marín López et al.
      Pages 229-265

    6. Generating VHDL Code from LOTOS Descriptions

      • Andrés Marín López, Carlos Delgado Kloos, Tomás Robles Valladares, Tomás de Miguel Moro
      Pages 266-293
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Keywords

About this book

Formal methods for hardware design still find limited use in industry. Yet current practice has to change to cope with decreasing design times and increasing quality requirements. This research report presents results from the Esprit project FORMAT (formal methods in hardware verification) which involved the collaboration of the enterprises Siemens, Italtel, Telefonica I+D, TGI, and AHL, the research institute OFFIS, and the universities of Madrid and Passau. The work presented involves advanced specification languages for hardware design that are intuitive to the designer, like timing diagrams and state based languages, as well as their relation to VHDL and formal languages like temporal logic and a process-algebraic calculus. The results of experimental tests of the tools are also presented.

Editors and Affiliations

  • Depto. Ingeniería, Universidad Carlos III de Madrid, Leganés/Madrid, Spain

    Carlos Delgado Kloos

  • Fachbereich Informatik, Abt. Rechnerarchitektur, Universität Oldenburg, Oldenburg, Germany

    Werner Damm

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