Design Methodology for Complex VLSI Devices

Abstract

In recent years the ratio between the design time of a new microelectronic component and its mean life on the market increased constantly. This was due to the growing complexity of the devices and components required by the market for the final applications. ASICs (Application Specific Integrated Circuits) and mixed hardware/software components are more and more measured in a range exceeding the 100/200 K-equivalent gates. While adequate manufacturing technologies have been introduced, the currently available ESDA (Electronic System Design Automation) tools have not kept the pace with market requirements. Even considering the advantages introduced by the wider and wider use of hardware description languages (basically Verilog and VHDL, with a predominance of the latter) for specification and simulation purposes, the vast majority of cost-effective circuit designs being done today using efficiently ESDA tools cannot exceed the limit of 100 K-equivalent gates. Obviously the industry and users are not satisfied with such a market offer, and the pressure on the ESDA vendors to develop new and more powerful system-level tools is strong. If this demand is not successfully answered, it is expected that serious bottlenecks in the design and production of complex systems in the near future will be directly linked to the failures of the proposed design methodologies and associated design flows.