Generating VHDL Code from LOTOS Descriptions

Abstract

The aim of this chapter is to describe an automatic technique for obtaining synthesizable VHDL code from a T-LOTOS specification. Although the technique is automated, some guidance from the user is always welcome when a better code is required. There are in principle two ways to perform the translation: translation of the T-LOTOS operators into VHDL code or substitution of T-LOTOS processes by corresponding VHDL blocks from a pre-defined T-LOTOS & VHDL library. Both procedures can could be also combined together. In the present chapter only the first approach is developed.