Abstract
In this chapter, three high-level reliability estimation techniques are illustrated which fast characterize the effects of errors on processor architecture.
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© 2018 Springer Science+Business Media Singapore
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Wang, Z., Chattopadhyay, A. (2018). Architectural Reliability Estimation. In: High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip. Computer Architecture and Design Methodologies. Springer, Singapore. https://doi.org/10.1007/978-981-10-1073-6_5
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DOI: https://doi.org/10.1007/978-981-10-1073-6_5
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Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-1072-9
Online ISBN: 978-981-10-1073-6
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