Analog Properties of Multi-Gate MOSFETs

Abstract

State-of-the-art high-k multi-gate CMOS technology is introduced in Chap. 2 with special focus on analog device behavior and variability. The specific impact of high-k dielectrics is also covered. The objective is to close the link from technology and integration aspects to analog device performance. The associated trade-offs are outlined. On device level, the reduction of short channel effects is a major advantage of fully depleted multi-gate devices, resulting in beneficial output impedance, gain and matching behavior. Serious concerns related to high-k dielectrics are pronounced flicker noise and dynamic threshold voltage variations or hysteresis effects. A novel model of this new hysteresis effects suitable for analog circuit simulation is derived and verified with measurements.