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Variation Aware Analog and Mixed-Signal Circuit Design in Emerging Multi-Gate CMOS Technologies

  • MichaelĀ Fulde

Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 28)

Table of contents

  1. Front Matter
    Pages I-X
  2. Michael Fulde
    Pages 1-14
  3. Michael Fulde
    Pages 15-31
  4. Michael Fulde
    Pages 33-55
  5. Michael Fulde
    Pages 57-97
  6. Michael Fulde
    Pages 99-109
  7. Michael Fulde
    Pages 111-113
  8. Back Matter
    Pages 115-127

About this book

Introduction

Since scaling of CMOS is reaching the nanometer area serious limitations enforce the introduction of novel materials, device architectures and device concepts. Multi-gate devices employing high-k gate dielectrics are considered as promising solution overcoming these scaling limitations of conventional planar bulk CMOS. Variation Aware Analog and Mixed-Signal Circuit Design in Emerging Multi-Gate CMOS Technologies provides a technology oriented assessment of analog and mixed-signal circuits in emerging high-k and multi-gate CMOS technologies. Closing the gap from technology to design a detailed insight into circuit performance trade-offs related to multi-gate and high-k device specifics is provided. The new effect of transient threshold voltage variations is described with an equivalent model that allows a systematic assessment of the consequences on circuit level and the development of countermeasures to compensate for performance degradation in comparators and A/D converters. Key analog, mixed-signal and RF building blocks are realized in high-k multi-gate technology and benchmarked against planar bulk. Performance and area benefits, enabled by advantageous multi-gate device properties are analytically and experimentally quantified for reference circuits, operational amplifiers and D/A converters. This is based on first time silicon investigations of complex mixed-signal building blocks as D/A converter and PLL with multi-gate devices. As another first, the integration of tunnel transistors in a multi-gate process is described, enabling devices with promising scaling and analog properties. Based on these devices a novel reference circuit is proposed which features low power consumption.

Keywords

CMOS FinFET Transistor field-effect transistor integrated circuit metal oxide semiconductur field-effect transistor micro-alloy transistor, MAT simulation

Authors and affiliations

  • MichaelĀ Fulde
    • 1
  1. 1.Infineon Technologies Austria AGVillachAustria

Bibliographic information

  • DOI https://doi.org/10.1007/978-90-481-3280-5
  • Copyright Information Springer Science+Business Media B.V. 2010
  • Publisher Name Springer, Dordrecht
  • eBook Packages Engineering
  • Print ISBN 978-90-481-3279-9
  • Online ISBN 978-90-481-3280-5
  • Series Print ISSN 1437-0387
  • Buy this book on publisher's site
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