Abstract
In this chapter, three architecture-level fault tolerant techniques are presented. In Sect. 6.1 opportunistic redundancy is proposed to protect the algorithmic units of embedded processor with a low performance penalty. In Sect. 6.2 asymmetric redundancy is proposed to protect the memory elements with the feature of unequal error protection based on information criticality. In Sect. 6.3 error confinement technique is proposed to correct errors in memory with statistical data, which reaches similar protection level with faster performance and less power consumption than traditional techniques.
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© 2018 Springer Science+Business Media Singapore
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Wang, Z., Chattopadhyay, A. (2018). Architectural Reliability Exploration. In: High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip. Computer Architecture and Design Methodologies. Springer, Singapore. https://doi.org/10.1007/978-981-10-1073-6_6
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DOI: https://doi.org/10.1007/978-981-10-1073-6_6
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Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-1072-9
Online ISBN: 978-981-10-1073-6
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