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Invasive Tightly Coupled Processor Arrays

Part of the book series: Computer Architecture and Design Methodologies ((CADM))

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Abstract

According to the International Technology Roadmap for Semiconductors(ITRS), the CMOS process technology trend in shrinking the feature sizes, as predicted by the Moore’s law [1], has led to significant improvements in the chip’s transistor density and achievable clock frequency.

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References

  1. Moore GE (1965) Cramming more components onto integrated circuits. Electronics 38(8)

    Google Scholar 

  2. Wgsimon (2015) Cpu transistor count & moore’s law. http://www.wikipedia.org. Accessed 10 Feb 2015

  3. Dennard RH, Gaensslen FH, Rideout VL, Bassous E, LeBlanc AR (1974) Design of ion-implanted mosfet’s with very small physical dimensions. IEEE J Solid-State Circuit 9(5): 256–268. ISSN 0018-9200. doi:10.1109/JSSC.1974.1050511

    Google Scholar 

  4. Borkar S (2007) Thousand core chips: a technology perspective. In: Proceedings of the 44th annual design automation conference (DAC) New York, NY, USA, 2007. ACM, pp 746–749. ISBN 978-1-59593-627-1. doi:10.1145/1278480.1278667

  5. Danowitz A, Kelley K, Mao J, Stevenson JP, Horowitz M (2012) Cpu db: recording microprocessor history. Commun ACM 55(4): 55–63. ISSN 0001-0782. doi:10.1145/2133806.2133822

    Google Scholar 

  6. Pop E (2010) Energy dissipation and transport in nanoscale devices. Nano Res 3(3):147–169. ISSN 1998-0124. doi:10.1007/s12274-010-1019-z

    Google Scholar 

  7. Ronen R, Mendelson A, Lai K, Lu SL, Pollack F, Shen JP (2001) Coming challenges in microarchitecture and architecture. Proc IEEE 89(3):325–340. ISSN 0018-9219. doi:10.1109/5.915377

    Google Scholar 

  8. Wolf W (2004) The future of multiprocessor systems-on-chips. In: Proceedings of the 41th annual design automation conference (DAC) pp 681–685

    Google Scholar 

  9. Wolf W, Jerraya AA, Martin G (2008) Multiprocessor system-on-chip (mpsoc) technology. IEEE Trans. Comput Aided Des Integr Circuits Syst 27(10):1701–1713. ISSN 0278-0070. doi:10.1109/TCAD.2008.923415

    Google Scholar 

  10. Kao J, Narendra S, Chandrakasan A (2002) Subthreshold leakage modeling and reduction techniques. In: Proceedings of the IEEE/ACM International conference on computer-aided design (ICCAD) pp 141–148. ACM. ISBN 0-7803-7607-2. doi:10.1145/774572.774593

  11. Homayoun H, Golshan S, Bozorgzadeh E, Veidenbaum A, Kurdahi FJ (2011) On leakage power optimization in clock tree networks for asics and general-purpose processors. Sustain Comput Inf Syst 1(1):75–87. ISSN 2210-5379. doi:10.1016/j.suscom.2010.10.005

    Google Scholar 

  12. Hosseinabady M, Nunez-Yanez JL (2012) Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles. IET Comput Digit Tech 6(1):1–11. ISSN 1751–8601. doi:10.1049/iet-cdt.2010.0097

    Google Scholar 

  13. Ost L, Mandelli M, Almeida GM, Moller L, Indrusiak LS, Sassatelli G, Benoit P, Glesner M, Robert M, Moraes F (2013) Power-aware dynamic mapping heuristics for noc-based mpsocs using a unified model-based approach. ACM Trans Embed Comput Syst 12(3):75:1–75:22. ISSN 1539-9087. doi:10.1145/2442116.2442125

    Google Scholar 

  14. Lee G, Choi K (2010) Thermal-aware fault-tolerant system design with coarse-grained reconfigurable array architecture. In: Proceedings of the NASA/ESA conference on adaptive hardware and systems (AHS) (AHS), IEEE, pp 265–272. ISBN 978-1-4244-5887-5. doi:10.1109/AHS.2010.5546249

  15. Singh AK, Shafique M, Kumar A, Henkel J (2013) Mapping on multi/many-core systems: survey of current and emerging trends. In: Proceedings of the 50th annual design automation conference(DAC) New York, NY, USA, 2013. ACM, pp1:1–1:10. ISBN 978-1-4503-2071-9. doi:10.1145/2463209.2488734

  16. Kalla R, Sinharoy B, Starke WJ, Floyd M (2010) Power7: IBM’s next-generation server processor. Micro IEEE 30(2):7 –15. ISSN 0272-1732. doi:10.1109/MM.2010.38

    Google Scholar 

  17. Howard J, Dighe S, Hoskote Y, Vangal S, Finan D, Ruhl G, Jenkins D, Wilson H, Borkar N, Schrom G, Pailet F, Jain S, Jacob T, Yada S, Marella S, Salihundam P, Erraguntla V, Konow M, Riepen M, Droege G, Lindemann J, Gries M, Apel T, Henriss K, Lund-Larsen T, Steibl S, Borkar S, De V, Van Der Wijngaart R, Mattson T (2010) A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS. In: Proceedings of 2010 IEEE international solid-state circuits conference digest of technical papers (ISSCC), pp108–109. ISBN 0193-6530. doi:10.1109/ISSCC.2010.5434077

  18. Duller A, Panesar G, Towner D (2003) Parallel Processing — the picoChip Way! In: Proceedings of communicating process architectures (CPA) Enschede, The Netherlands, pp 125–138. IOS Press

    Google Scholar 

  19. Tilera Corporation (2015) http://www.tilera.com. Accessed 10 Feb 2015

  20. Butts M (2007) Synchronization through communication in a massively parallel processor array. IEEE Micro 27(5):32–40

    Article  Google Scholar 

  21. Adapteva, Inc (2015) http://www.adapteva.com. Accessed 10 Feb 2015

  22. Motomura M (2002) A dynamically reconfigurable processor architecture. In: Microprocessor Forum, San Jose, CA, USA, In-Stat/MDR

    Google Scholar 

  23. Baumgarte V, Ehlers G, May F, Nückel A, Vorbach M, Weinhardt M (2003) PACT XPP—a self-reconfigurable data processing architecture. J Supercomputi 26:167–184. ISSN 0920-8542

    Google Scholar 

  24. Bouwens F, Berekovic M, De Sutter B, Gaydadjiev G (2008) Architecture enhancements for the adres coarse-grained reconfigurable array. In: Proceedings of the 3rd international conference on high performance embedded architectures and compilers (HiPEAC), Gothenburg, Springer, Sweden, pp 66–81. ISBN 3-540-77559-5, 978-3-540-77559-1

    Google Scholar 

  25. Goulding N, Sampson J, Venkatesh G, Garcia S, Auricchio J, Babb J, Taylor MB, Swanson S (2010) Greendroid: a mobile application processor for a future of dark silicon. In: Hot Chips 22

    Google Scholar 

  26. Taylor MB (2012) Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse. In: Proceedings of the 49th annual design automation conference (DAC), New York, NY, USA, ACM, pp 1131–1136. ISBN 978-1-4503-1199-1. doi:10.1145/2228360.2228567

  27. Carballo JA, Chan WTJ, Gargini PA, Kahng AB, Nath S (2014) ITRS 2.0: toward a re-framing of the semiconductor technology roadmap. In: 32nd IEEE international conference on computer design (iccd), 2014, pp 139–146. doi:10.1109/ICCD.2014.6974673

  28. Qualcomm I (2015) Snapdragon processors. https://www.qualcomm.com/products/snapdragon/processors. Accessed 10 Feb 2015

  29. ARM HI (2015) ARM processors. https://www.arm.com. Accessed 10 Feb 2015

  30. Xu C, Deng X, Zhang L, Fang J, Wang G, Jiang Y, Cao W, Che Y, Wang Y, Wang Z et al (2014) Collaborating cpu and gpu for large-scale high-order cfd simulations with complex grids on the tianhe-1a supercomputer. J Comput Phys 278:275–297. doi:10.1016/j.jcp.2014.08.024

    Article  Google Scholar 

  31. Kepler (2015). Nvidia processors. http://www.nvidia.com/object/nvidia-kepler.html. Accessed 10 Feb 2015

  32. Mukunoki D, Takahashi D (2013) Optimization of sparse matrix-vector multiplication for crs format on nvidia kepler architecture gpus. In: Computational science and its applications - ICCSA 2013. Lecture notes in computer science, vol. 7975. Springer, Berlin Heidelberg, pp 211–223. ISBN 978-3-642-39639-7. doi:10.1007/978-3-642-39640-3_15

    Google Scholar 

  33. Noll TG, von Sydow T, Neumann B, Schleifer J, Coenen T, Kappen G (2010) Reconfigurable components for application-specific processor architectures. In: Dynamically reconfigurable systems, Springer, pp 25–49. ISBN 978-90-481-3484-7. doi:10.1007/978-90-481-3485-4_2

    Google Scholar 

  34. DeHon A, Wawrzynek J (1999) Reconfigurable computing: what, why, and implications for design automation. In: Proceedings of the annual ACM/IEEE design automation conference (DAC) New York, NY, USA, June 1999. ACM, pp 610–615. ISBN 1-58113-109-7. doi:10.1145/309847.310009

  35. Calypto Design Systems Inc (2012) Calypto Product Family Datasheet

    Google Scholar 

  36. Impulse Accelerated Technologies. Impulse CoDeveloper C-to-FPGA Tools (2015) http://www.impulseaccelerated.com. Accessed 03 May 2015

  37. Hannig F, Ruckdeschel H, Dutta H, Teich J (2008) PARO: synthesis of hardware accelerators for multi-dimensional dataflow-intensive applications. In: Proceedings of the fourth international workshop on applied reconfigurable computing (ARC). Lecture notes in computer science(LNCS), vol 4943. Springer, pp 287–293. ISBN 978-3-540-78609-2. doi:10.1007/978-3-540-78610-8_30

  38. Püschel M, Franchetti F, Voronenko Y (2011) Encyclopedia of parallel computing. Springer, Heidelberg

    Google Scholar 

  39. Park Y, Park JJK, Mahlke S (2012) Efficient performance scaling of future cgras for mobile applications. In: International conference on field-programmable technology (FPT), 2012, pp 335–342. doi:10.1109/FPT.2012.6412158

  40. Singh H, Lee MH, Lu G, Kurdahi FJ, Bagherzadeh N, Chaves Filho EM (2000) MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications. Comput IEEE Trans 49(5):465–481. ISSN 0018-9340. doi:10.1109/12.859540

    Google Scholar 

  41. Dai P, Wang X, Zhang X, Zhao Q, Zhou Y, Sun Y (2009) A high power efficiency reconfigurable processor for multimedia processing. In: Proceedings of the IEEE 8th International conference on ASIC (ASICON) pp 67–70. doi:10.1109/ASICON.2009.5351604

  42. Khailany B, Dally WJ, Kapasi UJ, Mattson P, Namkoong J, Owens JD, Towles B, Chang A, Rixner S (2001) Imagine: media processing with streams. IEEE Micro 21(2):35–46. ISSN 0272-1732. http://doi.ieeecomputersociety.org/10.1109/40.918001

    Google Scholar 

  43. Kissler D, Strawetz A, Hannig F, Teich J (2009) Power-efficient reconfiguration control in coarse-grained dynamically reconfigurable architectures. In: Svensson L, Monteiro J (eds) Integrated circuit and system design. power and timing modeling, optimization and simulation. Lecture notes in computer science, vol 5349. Springer, Berlin, pp 307–317. ISBN 978-3-540-95947-2. doi:10.1007/978-3-540-95948-9_31

    Google Scholar 

  44. Hartenstein RW, Kress R (1995) A datapath synthesis system for the reconfigurable datapath architecture. In: Proceedings of the asia and south pacific design automation conference (ASP-DAC), pp 479–484. doi:10.1109/ASPDAC.1995.486359

  45. Becker J, Pionteck T, Glesner M (2000) DReAM: a dynamically reconfigurable architecture for future mobile communication applications. In: Hartenstein R, Grünbacher H (eds) Field-programmable logic and applications: the roadmap to reconfigurable computing. Lecture notes in computer science, vol 1896. Springer, Berlin, pp 312–321. ISBN 978-3-540-67899-1. doi:10.1007/3-540-44614-1_34

    Google Scholar 

  46. Waingold E, Taylor M, Srikrishna D, Sarkar, V, Lee W, Lee V, Kim J, Frank M, Finch P, Barua R et al (1997) Baring it all to software: raw machines. Comput 30(9):86–93. ISSN 0018-9162. doi:10.1109/2.612254

    Google Scholar 

  47. Karam LJ, AlKamal I, Gatherer A, Frantz GA, Anderson DV, Evans BL (2009) Trends in multicore dsp platforms. IEEE signal processing magazine. 26(6):38–49. ISSN 1053-5888. doi:10.1109/MSP.2009.934113

    Google Scholar 

  48. Kissler D, Strawetz A, Hannig F, Teich J (2008) Power-efficient reconfiguration control in coarse-grained dynamically reconfigurable architectures. In: Proceedings of the 18th International workshop on power and timing modeling, optimization and simulation (PATMOS). Lecture notes in computer science (LNCS), vol 5349. Springer, Lisbon, Portugal, pp 307–317. ISBN 978-3-540-95947-2. doi:10.1007/978-3-540-95948-9_31

    Google Scholar 

  49. Hannig F, Lari V, Boppu S, Tanase A, Reiche O (2014) Invasive tightly-coupled processor arrays: a domain-specific architecture/compiler co-design approach. ACM Trans Embed Comput Syst (TECS), 13(4s):133:1–133:29. doi:10.1145/2584660

    Google Scholar 

  50. Popovici K, Guerin X, Rousseau F, Paolucci PS, Jerraya AA (2008) Platform-based software design flow for heterogeneous MPSoC. ACM trans embed comput syst (TECS), 7(4):39:1–39:23. ISSN 1539-9087. doi:10.1145/1376804.1376807

    Google Scholar 

  51. Loka RR (2010) Serial computing is not dead

    Google Scholar 

  52. Diaz J, Munoz-Caro C, Nino A (2012) A survey of parallel programming models and tools in the multi and many-core era. IEEE trans parallel distrib syst (TPDS), 23(8):1369–1386. ISSN 1045-9219. doi:10.1109/TPDS.2011.308

    Google Scholar 

  53. Dutta H (2011) Synthesis and exploration of loop accelerators for systems-on-a-chip. PhD thesis, University of Erlangen-Nuremberg

    Google Scholar 

  54. Tullsen DM, Eggers SJ, Emer JS, Levy HM, Lo JL, Stamm RL (1996) Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor. SIGARCH Comput Archit News 24(2):191–202. ISSN 0163-5964. doi:10.1145/232974.232993

    Google Scholar 

  55. Mattson TG, Sanders BA, Massingill BL (2004) Patterns for parallel programming. Pearson Education

    Google Scholar 

  56. Bokhari SH (1988) Partitioning problems in parallel, pipeline, and distributed computing. IEEE Trans Comput 37(1):48–57. ISSN 0018-9340. doi:10.1109/12.75137

    Google Scholar 

  57. Kasim H, March V, Zhang R, See S (2008) Survey on parallel programming model. In: Cao J, Li M, Wu, MY, Chen J (eds) Network and parallel computing. Lecture notes in computer science, vol 5245. Springer, Berlin, pages 266–275. ISBN 978-3-540-88139-1. doi:10.1007/978-3-540-88140-7_24

    Google Scholar 

  58. Jalier C, Lattard D, Jerraya AA, Sassatelli G, Benoit P, Torres L (2010) Heterogeneous vs homogeneous mpsoc approaches for a mobile lte modem. In: Proceedings of the conference on design, automation and test in Europe (DATE), DATE ’10, 3001 Leuven, Belgium, Belgium, Mar. European Design and Automation Association, pp 184–189. ISBN 978-3-9810801-6-2. http://dl.acm.org/citation.cfm?id=1870926.1870971

  59. Bolchini C, Miele A (2013) Reliability-driven system-level synthesis for mixed-critical embedded systems. IEEE Trans Comput 62(12):2489–2502. ISSN 0018-9340. doi:10.1109/TC.2012.226

    Google Scholar 

  60. Gall H (2008) Functional safety iec 61508 / iec 61511 the impact to certification and the user. In: IEEE/ACS international conference on computer systems and applications, 2008. AICCSA 2008, pp 1027–1031. doi:10.1109/AICCSA.2008.4493673

  61. I. O. f. S. ISO (2011) International standard 26262: road vehicles functional safety. international standard

    Google Scholar 

  62. Kang SH, Yang H, Kim S, Bacivarov I, Ha S, Thiele L (2014) Reliability-aware mapping optimization of multi-core systems with mixed-criticality. In: Proceedings of design, automation and test in europe conference and exhibition (DATE), pp 1–4. doi:10.7873/DATE.2014.340

  63. Axer P, Sebastian M, Ernst R (2011) Reliability analysis for mpsocs with mixed-critical, hard real-time constraints. In: Proceedings of the 9th international conference on hardware/software codesign and system synthesis (CODES+ISSS), pp 149–158. ISBN 978-1-4503-0715-4

    Google Scholar 

  64. Cordes D, Heinig A, Marwedel P, Mallik A (2011) Automatic extraction of pipeline parallelism for embedded software using linear programming. In: Proceedings of the IEEE Iiternational conference on parallel and distributed systems(ICPADS), pp 699–706. doi:10.1109/ICPADS.2011.31

  65. Ceng J, Castrillón J, Sheng W, Scharwächter H, Leupers R, Ascheid G, Meyr H, Isshiki T, Kunieda H (2008) Maps: an integrated framework for mpsoc application parallelization. In: Proceedings of the 45th Annual design automation conference (DAC), DAC ’08, New York, NY, USA, ACM, pp 754–759. ISBN 978-1-60558-115-6. doi:10.1145/1391469.1391663

  66. Singh AK, Srikanthan T, Kumar A, Jigang W (2010) Communication-aware heuristics for run-time task mapping on noc-based mpsoc platforms. J Syst Archit (JSA), 56(7):242–255. ISSN 1383-7621. http://dx.doi.org/10.1016/j.sysarc.2010.04.007

    Google Scholar 

  67. Izosimov V, Pop P, Eles P, Peng Z (2005) Design optimization of time-and cost-constrained fault-tolerant distributed embedded systems. In: Proceedings of the conference on design, automation and test in Europe (DATE) Washington, DC, USA, IEEE Computer Society, pp 864–869. ISBN 0-7695-2288-2. doi:10.1109/DATE.2005.116

  68. Teich J (2008) Invasive algorithms and architectures. IT - Inf Technol 50(5):300–310

    Google Scholar 

  69. Henkel J, Herkersdorf A, Bauer L, Wild T, Hübner M, Pujari R, Grudnitsky A, Heisswolf J, Zaib A, Vogel B, Lari V, Kobbe S (2012) Invasive manycore architectures. In: Proceedings of the 17th Asia and South Pacific design automation conference (ASP-DAC), pp 193–200. doi:10.1109/ASPDAC.1995.486359

  70. Heisswolf J, Zaib A, Zwinkau A, Kobbe S, Weichslgartner A, Teich J, Henkel J, Snelting G, Herkersdorf A, Becker J (2014) CAP: communication aware programming. In: Proceedings of the 51th annual design automation conference (DAC), pp 105:1–105:6. doi:10.1145/2593069.2593103

  71. Tanase A, Lari V, Hannig F, Teich J (2013) Exploitation of quality/throughput tradeoffs in image processing through invasive computing. In: Proceedings of the international conference on parallel computing(ParCo), pp 53–62. doi:10.3233/978-1-61499-381-0-53

  72. Lari V, Narovlyanskyy A, Hannig F, Teich J (2011b) Decentralized dynamic resource management support for massively parallel processor arrays. In: Proceedings of the IEEE international conference on application-specific systems, architectures and processors (ASAP), IEEE computer society, pp 87–94. ISBN 978-1-4577-1291-3. doi:10.1109/ASAP.2011.6043240

  73. Lari V, Hannig F, Teich J (2011) Distributed resource reservation in massively parallel processor arrays. In: Proceedings of the international parallel and distributed processing symposium workshops (IPDPSW), IEEE computer society, pp 318–321. ISBN 978-0-7695-4385-7. doi:10.1109/IPDPS.2011.157

  74. Esmaeilzadeh H, Blem E, St Amant R, Sankaralingam K, Burger D (2011) Dark silicon and the end of multicore scaling. In: Proceedings of the 38th Annual international symposium on computer architecture (ISCA), IEEE, pp 7–18

    Google Scholar 

  75. Bircher WL, John L (2012) Predictive power management for multi-core processors. In: Varbanescu A, Molnos A, van Nieuwpoort R (eds) Computer architecture. Lecture notes in computer science, vol 6161. Springer, Berlin, pp 243–255. ISBN 978-3-642-24321-9. doi:10.1007/978-3-642-24322-6_21

    Google Scholar 

  76. Isci C, Contreras G, Martonosi M (2006) Live, runtime phase monitoring and prediction on real systems with application to dynamic power management. In: Proceedings of the 39th Annual IEEE/ACM international symposium on microarchitecture. MICRO 39, Washington, DC, USA, IEEE Computer Society, pp. 359–370. ISBN 0-7695-2732-9. doi:10.1109/MICRO.2006.30

  77. Isci C, Buyuktosunoglu A, Martonosi M (2005) Long-term workload phases: duration predictions and applications to DVFS. Micro IEEE 25(5):39–51. ISSN 0272-1732. doi:10.1109/MM.2005.93

    Google Scholar 

  78. Zompakis N, Bartzas A, Soudris D (2014) Using chaos theory based workload analysis to perform dynamic frequency scaling on mpsocs. J Syst Archit (JSA), 61(1):28–39. ISSN 1383-7621. http://dx.doi.org/10.1016/j.sysarc.2014.10.003. http://www.sciencedirect.com/science/article/pii/S1383762114001313

  79. Triki M, Wang Y, Ammari AC, Pedram M (2015) Hierarchical power management of a system with autonomously power-managed components using reinforcement learning. Integration, the VLSI J 48:10–20. ISSN 0167-9260. http://dx.doi.org/10.1016/j.vlsi.2014.06.001

    Google Scholar 

  80. Kissler D (2011) Power-efficient tightly-coupled processor arrays for digital signal processing. Dissertation, Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany

    Google Scholar 

  81. Kim Y, Mahapatra RN (2009) Dynamic context management for low power coarse-grained reconfigurable architecture. In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI (GLSVLSI), New York, NY, USA, ACM, pp 33–38. ISBN 978-1-60558-522-2. doi:10.1145/1531542.1531555

  82. Lari V, Muddasani S, Boppu S, Hannig F, Teich J (2012) Design of low power on-chip processor arrays. In: Proceedings of the 23rd IEEE International conference on application-specific systems, architectures, and processors (ASAP), IEEE computer society, pp 87–94. ISBN 978-0-7695-4768-8. doi:10.1109/ASAP.2012.10

  83. Lari V, Muddasani S, Boppu S, Hannig F, Schmid M, Teich J (2013) Hierarchical power management for adaptive tightly-coupled processor arrays. ACM trans des autom electron syst (TODAES), 18(1):2:1–2:25. doi:10.1145/2390191.2390193

    Google Scholar 

  84. Jacobs, A, Cieslewski G, George AD, Gordon-Ross A, Lam H (2012) Reconfigurable fault tolerance: a comprehensive framework for reliable and adaptive FPGA-based space computing. ACM trans reconfigurable technol syst(TRETS), 5(4):21:1–21:30, ISSN 1936-7406. doi:10.1145/2392616.2392619

    Google Scholar 

  85. Schweizer T, Schlicker P, Eisenhardt S, Kuhn T, Rosenstiel W (2011) Low-cost tmr for fault-tolerance on coarse-grained reconfigurable architectures. In: Proceedings of the international conference on reconfigurable computing and FPGAs (ReConFig), pp 135–140. doi:10.1109/ReConFig.2011.57

  86. Gong C, Melhem R, Gupta R (1996) Loop transformations for fault detection in regular loops on massively parallel systems. IEEE Trans. Parallel Distrib Syst 7(12):1238–1249. ISSN 1045-9219. doi:10.1109/71.553273

    Google Scholar 

  87. Han K, Lee G, Choi K (2014) Software-level approaches for tolerating transient faults in a coarse-grainedreconfigurable architecture. IEEE transactions on dependable and secure comput, 11(4):392–398. ISSN 1545-5971. doi:10.1109/TDSC.2013.54

    Google Scholar 

  88. Witterauf M, Tanase A, Lari V, Teich J, Snelting G, Zwinkau A (2015) Adaptive fault tolerance through invasive computing. In: Proceedings of the NASA/ESA conference on adaptive hardware and systems (AHS)

    Google Scholar 

  89. Lari V, Tanase A, Teich J, Witterauf M, Khosravi F, Hannig F, Meyer B (2015) Co-design approach for fault-tolerant loop execution on coarse-grained reconfigurable arrays. In: Proceedings of the NASA/ESA conference on adaptive hardware and systems (AHS)

    Google Scholar 

  90. Tanase A, Witterauf M, Teich J, Hannig F, Lari V (2015)On-demand fault-tolerant loop processing on massively parallel processor arrays. In: Proceedings of the IEEE international conference on application-specific systems, architectures and processors (ASAP)

    Google Scholar 

  91. Lari V, Tanase A, Hannig F, Teich J (2014) Massively parallel processor architectures for resource-aware computing. In: Proceedings of the first workshop on resource awareness and adaptivity in multi-core computing(Racing). pp 1–7

    Google Scholar 

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    Vahid Lari

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Lari, V. (2016). Introduction. In: Invasive Tightly Coupled Processor Arrays. Computer Architecture and Design Methodologies. Springer, Singapore. https://doi.org/10.1007/978-981-10-1058-3_1

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