Abstract
This chapter deals with the modeling of Cu-based on-chip interconnects. The model considers the nonlinear effects of CMOS driver as well as the transmission line effects of interconnect line. The CMOS driver is represented by the nth power law model and the coupled-multiple interconnect lines are modeled by the FDTD technique. The model is validated by the industry standard HSPICE simulator. It is observed that the results of the proposed model closely match with that of HSPICE simulations. Encouragingly, the proposed model is highly time efficient than the HSPICE.
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Kaushik, B.K., Kumar, V.R., Patnaik, A. (2016). FDTD Model for Crosstalk Analysis of CMOS Gate-Driven Coupled Copper Interconnects. In: Crosstalk in Modern On-Chip Interconnects. SpringerBriefs in Applied Sciences and Technology. Springer, Singapore. https://doi.org/10.1007/978-981-10-0800-9_3
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DOI: https://doi.org/10.1007/978-981-10-0800-9_3
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