Abstract
Many processes performed during the fabrication of microelectronic circuits result in changes in the shape and/or composition of the wafer surface. This is particularly true of deposition, etch and ‘planarization’ steps; e.g., thin film flow (or ‘reflow’) and chemical mechanical polishing (CMP) steps. It is well known that differences in the surface shape and/or composition (referred to as ‘topography’ in this chapter) at one or more critical steps in the process flow can result in significant differences in circuit yield and performance; particularly for advanced device structures. The importance of topography relevant steps in determining device and circuit performance explains the widespread interest in simulations of the time evolution of topography during deposition, etch and planarization processes.
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Cale, T.S., Mahadev, V., Tang, Z., Rajagopalan, G., Borucki, L.J. (1997). Topography Evolution During Semiconductor Processing. In: Williams, P.F. (eds) Plasma Processing of Semiconductors. NATO ASI Series, vol 336. Springer, Dordrecht. https://doi.org/10.1007/978-94-011-5884-8_6
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DOI: https://doi.org/10.1007/978-94-011-5884-8_6
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