POINT DEFECTS IN Si-SiO₂ SYSTEMS: CURRENT UNDERSTANDING

Abstract

Perhaps no other technology developed in the 20^th century plays such an important role on the daily life of today’s civilized society as microelectronics. The rapid growth experienced by complementary-metal-oxide-semiconductor (CMOS) technology since the first metal-oxide semiconductor field effect transistor (MOSFET) was realized by Kahng [1] some 40 years ago, accompanied by the advances in integrated circuit (IC) fabrication, has been revolutionizing the field of electronics. The past thirty years have also witnessed tremendous progress toward the miniaturization of CMOS devices, a trend that continues toward further downscaling of the device feature size. While miniaturization of CMOS devices has resulted in higher packing density (more devices per unit area), higher circuit speed (faster computers), and lower power dissipation, it has also created new problems and issues that need resolution for the reliability of the contemporary and future generation technology. In order to appreciate the problems and reliability issues associated with the steady downscaling of CMOS devices, a schematic design of a MOSFET is shown in Fig. 1. The top metal, generally a polycrystalline-silicon (poly-Si) acts as a gate. A thin amorphous SiO¹ dielectric layer underneath the gate electrode, normally referred to as the “gate oxide”, lies above the channel regions which separates the “source” (carrier donor) and the “drain” (carrier acceptor) layers. The distance between the source and the drain under the gate dielectric is called the “channel length”. Upon biasing the gate electrode, an image charge builds up under the gate initially forming a “depletion region” and eventually at a certain voltage (called the threshold voltage, V_th) inverts the silicon surface and current starts flowing in the channel between the source and the drain. “Decreasing the feature size” of MOSFET generally means reducing the channel length. The shorter the channel length, the faster the carrier flow and the higher the drive current resulting in higher speed. Also, continued reduction in the supply voltage has lowered power consumption. Of course with the miniaturization of the device components, the primary benefit is that much larger numbers of transistors can be integrated per unit area on the wafer, thus increasing the device density in very large integrated circuits (VLSI). Such desirable features have been the driving force toward miniaturization of the MOSFET.