Abstract
Integrated circuits are susceptible to dynamic variations in supply voltage (VCC) and temperature. Abrupt changes in die-level switching activity induce large current transients in the power delivery system, resulting in VCC droop and overshoot fluctuations. The magnitude and duration of VCC droops and overshoots depend on the interaction of capacitive and inductive parasitics at the board, package, and die levels with changes in current demand [1]. Temperature variations depend on workload, environmental conditions, and the heat-removal capability of the package. These dynamic variations in VCC and temperature degrade the clock frequency (FCLK) of microprocessors. Conventional designs build a guardband into the operating FCLK to ensure correct functionality within the presence of worst-case dynamic variations. Consequently, these inflexible designs cannot exploit opportunities for higher performance by increasing FCLK or lower power by lowering VCC during favorable operating conditions. Since most systems usually operate at nominal conditions where worst-case scenarios rarely occur, these infrequent dynamic variations severely limit the performance and energy efficiency of conventional microprocessor designs.
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Bowman, K.A., Tschanz, J.W. (2010). Resilient Circuits for Dynamic Variation Tolerance. In: Amara, A., Ea, T., Belleville, M. (eds) Emerging Technologies and Circuits. Lecture Notes in Electrical Engineering, vol 66. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9379-0_11
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