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Abstract

As very diverse applications have to be executed in the same computational structure, the pressure for dynamic modifications in the reconfigurable logic increases, since fast adaptability is key to sustain fast execution with the lowest possible power dissipation. This proves that the main strategy to bring reconfigurable systems to be used as mainstream computing is to rely on dynamic optimization techniques, such as the ones already presented. Therefore, in this chapter two approaches that use reconfigurable fabric together with a mechanism that somehow reassembles the behavior of the dynamic optimization techniques are discussed, as well as their basic structure, granularity, communication issues, how the binary translation mechanism works and their potential gains in performance and energy.

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References

  1. Clark, N., Blome, J., Chu, M., Mahlke, S., Biles, S., Flautner, K.: An architecture framework for transparent instruction set customization in embedded processors. In: ISCA ’05: Proceedings of the 32nd Annual International Symposium on Computer Architecture, pp. 272–283. IEEE Computer Society, Los Alamitos (2005). doi:10.1109/ISCA.2005.9

    Google Scholar 

  2. Clark, N., Kudlur, M., Park, H., Mahlke, S., Flautner, K.: Application-specific processing on a general-purpose core via transparent instruction set customization. In: MICRO 37: Proceedings of the 37th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 30–40. IEEE Computer Society, Los Alamitos (2004). doi:10.1109/MICRO.2004.5

    Google Scholar 

  3. Clark, N., Tang, W., Mahlke, S.: Automatically generating custom instruction set extensions. In: Workshop on Application-Specific Processors (WASP), pp. 94–101 (2002)

    Google Scholar 

  4. Clark, N., Zhong, H., Mahlke, S.: Processor acceleration through automated instruction set customization. In: MICRO 36: Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, p. 129. IEEE Computer Society, Los Alamitos (2003)

    Google Scholar 

  5. Clark, N.T., Zhong, H.: Automated custom instruction generation for domain-specific processor acceleration. IEEE Trans. Comput. 54(10), 1258–1270 (2005). doi:10.1109/TC.2005.156. Member-Mahlke, Scott A.

    Article  Google Scholar 

  6. Hwu, W.M.W., Mahlke, S.A., Chen, W.Y., Chang, P.P., Warter, N.J., Bringmann, R.A., Quellette, R.G., Hank, R.E., Kiyohara, T., Haab, G.E., Holm, J.G., Lavery, D.M.: The superblock: an effective technique for vliw and superscalar compilation. In: Instruction-level Parallel Processors, pp. 234–253 (1995)

    Google Scholar 

  7. Lee, C., Potkonjak, M., Mangione-smith, W.H.: Mediabench: A tool for evaluating and synthesizing multimedia and communications systems. In: International Symposium on Microarchitecture, pp. 330–335 (1997)

    Google Scholar 

  8. Lysecky, R., Stitt, G., Vahid, F.: Warp processors. ACM Trans. Des. Autom. Electron. Syst. 11(3), 659–681 (2006). doi:10.1145/1142980.1142986

    Article  Google Scholar 

  9. Lysecky, R., Vahid, F.: A configurable logic architecture for dynamic hardware/software partitioning. In: DATE ’04: Proceedings of the Conference on Design, Automation and Test in Europe, p. 10480. IEEE Computer Society, Los Alamitos (2004)

    Google Scholar 

  10. Lysecky, R., Vahid, F.: A study of the speedups and competitiveness of fpga soft processor cores using dynamic hardware/software partitioning. In: DATE ’05: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 18–23. IEEE Computer Society, Los Alamitos (2005). doi:10.1109/DATE.2005.38

    Google Scholar 

  11. Lysecky, R., Vahid, F.: Design and implementation of a MicroBlaze-based warp processor. ACM Trans. Embed. Comput. Syst. 8(3), 1–22 (2009). doi:10.1145/1509288.1509294

    Article  Google Scholar 

  12. Memik, G., Mangione-Smith, W.H., Hu, W.: NetBench: a benchmarking suite for network processors. In: ICCAD ’01: Proceedings of the 2001 IEEE/ACM International Conference on Computer-aided Design, pp. 39–42. IEEE Press, New York (2001)

    Google Scholar 

  13. Patel, S.J., Lumetta, S.S.: Replay: A hardware framework for dynamic optimization. IEEE Trans. Comput. 50(6), 590–608 (2001). doi:10.1109/12.931895

    Article  Google Scholar 

  14. Rotenberg, E., Bennett, S., Smith, J.E.: Trace cache: a low latency approach to high bandwidth instruction fetching. In: MICRO 29: Proceedings of the 29th Annual ACM/IEEE International Symposium on Microarchitecture, pp. 24–35. IEEE Computer Society, Los Alamitos (1996)

    Chapter  Google Scholar 

  15. Stitt, G., Lysecky, R., Vahid, F.: Dynamic hardware/software partitioning: a first approach. In: DAC ’03: Proceedings of the 40th Annual Design Automation Conference, pp. 250–255. ACM, New York (2003). doi:10.1145/775832.775896

    Google Scholar 

  16. Stitt, G., Vahid, F., McGregor, G., Einloth, B.: Hardware/software partitioning of software binaries: a case study of h.264 decode. In: CODES+ISSS ’05: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp. 285–290. ACM, New York (2005). doi:10.1145/1084834.1084905

    Chapter  Google Scholar 

  17. Vahid, F., Stitt, G., Lysecky, R.: Warp processing: Dynamic translation of binaries to fpga circuits. Computer 41(7), 40–46 (2008). doi:10.1109/MC.2008.240

    Article  Google Scholar 

  18. Yu, P., Mitra, T.: Characterizing embedded applications for instruction-set extensible processors. In: DAC ’04: Proceedings of the 41st Annual Design Automation Conference, pp. 723–728. ACM, New York (2004). doi:10.1145/996566.996764

    Chapter  Google Scholar 

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Correspondence to Antonio Carlos Schneider Beck Fl. .

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Schneider Beck Fl., A.C., Carro, L. (2010). Dynamic Detection and Reconfiguration. In: Dynamic Reconfigurable Architectures and Transparent Optimization Techniques. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3913-2_5

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  • DOI: https://doi.org/10.1007/978-90-481-3913-2_5

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