Abstract
This introductory chapter presents several challenges that architectures are facing these days, such as the imminent end of the Moore’s law as it is known today; the usage of future technologies that will replace silicon; the stagnation of ILP increase in superscalar processors and their excessive power consumption and, most importantly, how the aforementioned aspects are impacting on the development of new architectural alternatives. All these aspects point to the fact that new architectural solutions are necessary. Then, the main reasons that motivated the writing of this book are shown. Several aspects are discussed, as the why ILP does not increase as before; the use of both combinational logic and reconfigurable fabric to speedup execution of data dependent instructions; the importance of maintaining binary compatibility, which is the possibility of reusing previously compiled code without any kind of modification; yield issues and the costs of fabrication. This chapter ends with a brief review of what will be seen in the rest of the book.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Austin, T., Blaauw, D., Mahlke, S., Mudge, T., Chakrabarti, C., Wolf, W.: Mobile supercomputers. Computer 37(5), 81–83 (2004). doi:10.1109/MC.2004.1297253
Burger, D., Goodman, J.R.: Billion-transistor architectures: There and back again. Computer 37(3), 22–28 (2004). doi:10.1109/MC.2004.1273999
Burns, J., Gaudiot, J.L.: Smt layout overhead and scalability. IEEE Trans. Parallel Distrib. Syst. 13(2), 142–155 (2002). doi:10.1109/71.983942
Conte, G., Tommesani, S., Zanichelli, F.: The long and winding road to high-performance image processing with mmx/sse. In: CAMP’00: Proceedings of the Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP’00), p. 302. IEEE Computer Society, Los Alamitos (2000)
Flynn, M.J., Hung, P.: Microprocessor design issues: Thoughts on the road ahead. IEEE Micro 25(3), 16–31 (2005). doi:10.1109/MM.2005.56
Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach, 4th edn. Morgan Kaufmann, San Mateo (2006)
Kim, N.S., Austin, T., Blaauw, D., Mudge, T., Flautner, K., Hu, J.S., Irwin, M.J., Kandemir, M., Narayanan, V.: Leakage current: Moore’s law meets static power. Computer 36(12), 68–75 (2003). doi:10.1109/MC.2003.1250885
Koufaty, D., Marr, D.T.: Hyperthreading technology in the netburst microarchitecture. IEEE Micro 23(2), 56–65 (2003)
McLellan, E.J., Webb, D.A.: The alpha 21264 microprocessor architecture. In: ICCD’98: Proceedings of the International Conference on Computer Design, p. 90. IEEE Computer Society, Los Alamitos (1998)
Prakash, T.K., Peng, L.: Performance characterization of spec cpu2006 benchmarks on Intel core 2 duo processor. ISAST Trans. Comput. Softw. Eng. 2(1), 36–41 (2008)
Rutenbar, R.A., Baron, M., Daniel, T., Jayaraman, R., Or-Bach, Z., Rose, J., Sechen, C.: (when) will fpgas kill asics? (panel session). In: DAC’01: Proceedings of the 38th Annual Design Automation Conference, pp. 321–322. ACM, New York (2001). doi:10.1145/378239.378499
Semiconductors, T.I.T.R.: Itrs 2008 edition. Tech. Rep., ITRS (2008). http://www.itrs.net
Sima, D.: Decisive aspects in the evolution of microprocessors. Proc. IEEE 92(12), 1896–1926 (2004)
Thompson, S., Parthasarathy, S.: Moore’s law: The future of si microelectronics. Mater. Today 9(6), 20–25 (2006)
Thompson, S.E., Chau, R.S., Ghani, T., Mistry, K., Tyagi, S., Bohr, M.T.: In search of “forever,” continued transistor scaling one new material at a time. IEEE Trans. Semicond. Manuf. 18(1), 26–36 (2005). doi:10.1109/TSM.2004.841816
Vahid, F.: The softening of hardware. Computer 36(4), 27–34 (2003). doi:10.1109/MC.2003.1193225
Vahid, F.: It’s time to stop calling circuits “hardware”. Computer 40(9), 106–108 (2007). doi:10.1109/MC.2007.322
Vahid, F., Lysecky, R.L., Zhang, C., Stitt, G.: Highly configurable platforms for embedded computing systems. Microelectron. J. 34(11), 1025–1029 (2003)
Wall, D.W.: Limits of instruction-level parallelism. In: ASPLOS-IV: Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 176–188. ACM, New York (1991). doi:10.1145/106972.106991
Wilcox, K., Manne, S.: Alpha processors: A history of power issues and a look to the future. In: Proceedings of the Cool-Chips Tutorial. Held in Conjunction with the International Symposium on Microarchitecture. ACM/IEEE, New York (1999)
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2010 Springer Science+Business Media B.V.
About this chapter
Cite this chapter
Schneider Beck Fl., A.C., Carro, L. (2010). Introduction. In: Dynamic Reconfigurable Architectures and Transparent Optimization Techniques. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3913-2_1
Download citation
DOI: https://doi.org/10.1007/978-90-481-3913-2_1
Published:
Publisher Name: Springer, Dordrecht
Print ISBN: 978-90-481-3912-5
Online ISBN: 978-90-481-3913-2
eBook Packages: EngineeringEngineering (R0)