Abstract
With the challenges of keeping testing costs down, DFT-based testing methods have been pursued [6–9, 47, 48]. The timing margining test is one of the widely adopted DFT methods by companies [8, 9]. Usually facilitated by a loopback on-die or off-die, the idea is to assess the margin in a given I/O’s timing and make the pass/fail decision. This test coupled with additional DFT testing methods (e.g. DFT specific to clock data recovery circuitry as noted in [9]) enables computer product manufacturers to ignore the communications style testing, which involves expensive ATE equipment and long testing times. Still, there continues to be one nagging question, “Are we missing anything gross by relying heavily upon timing margining test?”
We decided to study this question and this chapter summarizes our results. The next section gives a primer on timing margining. The core of the chapter explains the testing method’s gap, which include random jitter, non-linear clock recovery circuitry, jitter amplification, and duty cycle distortion.
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Hong, D., Cheng, KT. (2010). Gaps in Timing Margining Test. In: Efficient Test Methodologies for High-Speed Serial Links. Lecture Notes in Electrical Engineering, vol 51. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3443-4_5
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DOI: https://doi.org/10.1007/978-90-481-3443-4_5
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