Gaps in Timing Margining Test

Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 51)


With the challenges of keeping testing costs down, DFT-based testing methods have been pursued [6–9, 47, 48]. The timing margining test is one of the widely adopted DFT methods by companies [8, 9]. Usually facilitated by a loopback on-die or off-die, the idea is to assess the margin in a given I/O’s timing and make the pass/fail decision. This test coupled with additional DFT testing methods (e.g. DFT specific to clock data recovery circuitry as noted in [9]) enables computer product manufacturers to ignore the communications style testing, which involves expensive ATE equipment and long testing times. Still, there continues to be one nagging question, “Are we missing anything gross by relying heavily upon timing margining test?”

We decided to study this question and this chapter summarizes our results. The next section gives a primer on timing margining. The core of the chapter explains the testing method’s gap, which include random jitter, non-linear clock recovery circuitry, jitter amplification, and duty cycle distortion.


  1. 6.
    Sunter S, Roy A (July–Aug 2004) On-chip digital jitter measurement, from megahertz to gigahertz. IEEE Des Test Comp 21(4):314–321CrossRefGoogle Scholar
  2. 7.
    Chan AH, Roberts GW (Jan 2004) A jitter characterization system using component-invariant vernier delay line. IEEE Trans Very Large Scale Integr (VLSI) Sys 12(1):79–95CrossRefGoogle Scholar
  3. 8.
    Mak TM et al. (July–Aug 2004) Testing Gbps interfaces without a gigahertz tester. IEEE Des Test Comp 21(4):278–286CrossRefGoogle Scholar
  4. 9.
    Robertson I et al. (Nov 2005) Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems. In: Proceedings of International Test Conference, pp 1–8Google Scholar
  5. 22.
    Cai Y et al. (Jan–Feb 2002) Jitter testing for gigabit serial communication transceivers, IEEE Des Test Comp. 19:66–74CrossRefGoogle Scholar
  6. 27.
    Agilent Technologies, Jitter Analysis: The dual-Dirac Model, RJ/DJ, and Q-Scale, White Paper. Available at
  7. 44.
    Lee J et al. (Sept 2004) Analysis and modeling of bang–bang clock and data recovery circuits. IEEE J Solid State Circuit 39(9):1571–1580CrossRefGoogle Scholar
  8. 45.
    Walker RC (2003) Designing bang–bang plls for clock and data recovery in serial data transmission systems. In: Razavi B (ed) Phase-locking in high-performance systems, IEEE Press, New York, pp 34–45Google Scholar
  9. 46.
    Choi Y et al. (Nov 2003) Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery. IEEE Trans Circuit Syst II 50(11):775–783CrossRefGoogle Scholar
  10. 47.
    Provost B et al. (Oct 2004) PAC IO loopback design for high speed /spl mu/processor IO test. In: Proceedings of International Test Conference, pp 23–30Google Scholar
  11. 48.
    Sunter S, Roy A (Oct 2005) Structural tests for jitter tolerance in SerDes receivers. In: Proceedings of International Test Conference, pp 1–10Google Scholar
  12. 49.
    Nejedlo JJ (Oct 2003) IBISTTM (Interconnect Built-In Self-Test) architecture and methodology for PCI Express: Intel’s next-generation test and validation methodology for performance IO. In: Proceedings of International Test Conference, pp 784–793Google Scholar
  13. 50.
    Kim J (2002) Design of CMOS adaptive-supply serial links, Ph.D. thesis, Stanford University, CaliforniaGoogle Scholar
  14. 51.
    Shimanachi M (Oct 2001) An approach to consistent jitter modeling for various jitter aspects and measurement methods. In: Proceedings of International Test Conference, pp 845–857Google Scholar
  15. 52.
    Balamurugan G, Shanbhag N (Aug 2003) Modeling and mitigation of jitter in high-speed source-synchronous inter-chip communication systems. In: Proceedings of Asilomar Conference on Signals, Systems and Computers, pp 1681–1687Google Scholar
  16. 53.
    Sidiropoulos S, Horowitz MA, semidigital A (Nov 1997) Dual delay-locked loop. IEEE J Solid State Circuit 32(11):1683–1692CrossRefGoogle Scholar
  17. 54.
    Lee TH, Bulzacchelli JF (Dec 1992) A 155-MHz clock recovery delay- and phase-locked loop. IEEE J Solid State Circuit 27(12):1736–1746CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  1. 1.Broadcom CorporationIrvineUSA
  2. 2.Santa Barbara College of Engineering Dept. Electrical & Computer EngineeringUniversity of CaliforniaSanta BarbaraUSA

Personalised recommendations