Abstract
All the architectures proposed in the previous chapters have been realized using the bit-sliced design paradigm. The architectures are very regular in their structures, thereby serving as a motivation to automate the generation of the arithmetic circuit descriptions for the target FPGA platform. In this chapter, we will introduce the proposed CAD tool for design automation named FlexiCore. We also present two relevant case studies comprising of multiple modules, whose HDL and placement constraints can be generated using FlexiCore.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Amira, A., Bensaali, F.: An FPGA based parameterisable system for matrix product implementation. In: IEEE Workshop on Signal Processing Systems (SiPS), pp. 75–79 (2002)
Amira, A., Bouridane, A., Milligan, P., Sage, P.: A high throughput FPGA implementation of a bit-level matrix product. In: IEEE Workshop on Signal Processing Systems (SiPS), pp. 356–364 (2000)
Brent, R.P., Kung, H.T.: A systolic algorithm for integer GCD computation. In: IEEE 7th Symposium on Computer Arithmetic (ARITH), pp. 118–125 (1985)
Hormigo, J., Caffarena, G., Oliver, J.P., Boemo, E.: Self-reconfigurable constant multiplier for FPGA. ACM Trans. Reconfigurable Technol. Syst. 6(3), 14.1–14.17 (2013)
Kumm, M., Moller, K., Zipf, P.: Dynamically reconfigurable FIR filter architectures with fast reconfiguration. In: 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), pp.1–8 (2013)
Kumm, M., Moller, K., Zipf, P.: Partial LUT size analysis in distributed arithmetic FIR filter on FPGAs. In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2054–2057 (2013)
Kumm, M., Moller, K., Zipf, P.: Reconfigurable FIR filter using distributed arithmetic on FPGAs. In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2058–2061 (2013)
Meyer-Baese, U.: Digital Signal Processing with Field Programmable Gate Arrays. Signals and Communication Technology, 3rd edn. Springer, New York (2007)
Parhi, K.K.: VLSI Digital Signal Processing Systems: Design and Implementation. Wiley, New York (2007)
Stehlé, D., Zimmermann, P.: A binary recursive Gcd algorithm. In: Proceedings of ANTS’04. Lecture Notes in Computer Science, vol. 3076, pp. 411–425, Springer (2004)
White, S.A.: Applications of distributed arithmetic to digital signal processing: a tutorial review. IEEE ASSP Mag. 6(3), 4–19 (1989)
Wirthlin, M.J.: Constant coefficient multiplication using look-up tables. J. VLSI Signal Process. Syst. 36(1), 7–15 (2004)
Xilinx Inc.: Virtex-5 libraries guide for HDL designs. UG621 (v11.3). http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/virtex5_hdl.pdf. Accessed 6 Sept 2009
Yang, Y., Zhao, W., Inoue, Y.: High-performance systolic arrays for band matrix multiplication. In: IEEE International Symposium on Circuits and Systems (ISCAS), vol. 2, pp. 1130–1133 (2005)
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2016 Springer India
About this chapter
Cite this chapter
Palchaudhuri, A., Chakraborty, R.S. (2016). Design Automation and Case Studies. In: High Performance Integer Arithmetic Circuit Design on FPGA. Springer Series in Advanced Microelectronics, vol 51. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2520-1_7
Download citation
DOI: https://doi.org/10.1007/978-81-322-2520-1_7
Published:
Publisher Name: Springer, New Delhi
Print ISBN: 978-81-322-2519-5
Online ISBN: 978-81-322-2520-1
eBook Packages: EngineeringEngineering (R0)