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Architecture of Controlpath Circuits

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High Performance Integer Arithmetic Circuit Design on FPGA

Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 51))

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Abstract

This chapter explores the mathematical analyses and bit-sliced architectures of the pipelined implementations of two controlpath circuits: integer comparator and loadable bidirectional counter supported by the FlexiCore CAD tool currently.

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References

  1. Perri, S., Zicari, P., Corsonello, P.: Efficient absolute difference circuits in Virtex-5 FPGAs. In: Proceedings of the15th IEEE Mediterranean Electrotechnical Conference (MELECON), pp. 309–313 (2010)

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  2. Stan, M.R., Tenca, A.F., Ercegovac, M.D.: Long and fast up/down counters. IEEE Trans. Comput. 47(7), 722–735 (1998)

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  3. Xilinx Inc.: Virtex-5 libraries guide for HDL designs, UG621 (v11.3). http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/virtex5_hdl.pdf Cited 6 Sep 2009

  4. Xilinx Inc.: Virtex-5 FPGA xtremeDSP design considerations user guide, UG193 (v3.5). http://www.xilinx.com/support/documentation/user_guides/ug193.pdf Cited 26 Jan 2012

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Correspondence to Ayan Palchaudhuri .

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Palchaudhuri, A., Chakraborty, R.S. (2016). Architecture of Controlpath Circuits. In: High Performance Integer Arithmetic Circuit Design on FPGA. Springer Series in Advanced Microelectronics, vol 51. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2520-1_5

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  • DOI: https://doi.org/10.1007/978-81-322-2520-1_5

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  • Publisher Name: Springer, New Delhi

  • Print ISBN: 978-81-322-2519-5

  • Online ISBN: 978-81-322-2520-1

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