Abstract
This chapter elaborates on some useful guidelines that can be helpful for compact and high-performance realization of circuits on modern high-end FPGAs from Xilinx. It involves manipulation of the Boolean equations a priori in the HDL circuit descriptions to forms that can be optimally mapped to the native target architecture by the CAD software. Although the guidelines are relatively simple, they are extremely useful in the efficient realization of numerous arithmetic circuits which can be constructed using the “bit-sliced” design paradigm.
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Palchaudhuri, A., Chakraborty, R.S. (2016). A Fabric Component Based Design Approach for High-Performance Integer Arithmetic Circuits. In: High Performance Integer Arithmetic Circuit Design on FPGA. Springer Series in Advanced Microelectronics, vol 51. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2520-1_3
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DOI: https://doi.org/10.1007/978-81-322-2520-1_3
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