A Fabric Component Based Design Approach for High-Performance Integer Arithmetic Circuits
This chapter elaborates on some useful guidelines that can be helpful for compact and high-performance realization of circuits on modern high-end FPGAs from Xilinx. It involves manipulation of the Boolean equations a priori in the HDL circuit descriptions to forms that can be optimally mapped to the native target architecture by the CAD software. Although the guidelines are relatively simple, they are extremely useful in the efficient realization of numerous arithmetic circuits which can be constructed using the “bit-sliced” design paradigm.
KeywordsBoolean Function Equality Check Single Slice Arithmetic Circuit Boolean Equation
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