Accurate Layout-Based Interconnect Analysis

Abstract

We have developed a set of simulation programs for two- and three-dimensional analysis of interconnect structures. The simulators are based on the finite element method and can be used for highly accurate capacitance extraction, resistance calculation, transient electric simulation (calculation of capacitive crosstalk and delay times), and coupled electro-thermal simulations. The layout of the interconnect structure can be imported from CIF or GDSII files, or can be created interactively with a graphical layout editor [1] which is also used to select an “area of interest” and to generate cuts for two-dimensional simulations. The geometric structure can be generated either directly from the layout by specifying constant layer thicknesses, or by a rigorous topography simulation [2]. For the creation of two-dimensional simulation grids the program Triangle [3] is used, for the three-dimensional case we perform a layer-based grid generation method [4]. As application example a polysilicon resistor pair is analyzed with the tools presented.