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Accurate Layout-Based Interconnect Analysis

  • R. Sabelka
  • R. Martins
  • S. Selberherr
Conference paper

Abstract

We have developed a set of simulation programs for two- and three-dimensional analysis of interconnect structures. The simulators are based on the finite element method and can be used for highly accurate capacitance extraction, resistance calculation, transient electric simulation (calculation of capacitive crosstalk and delay times), and coupled electro-thermal simulations. The layout of the interconnect structure can be imported from CIF or GDSII files, or can be created interactively with a graphical layout editor [1] which is also used to select an “area of interest” and to generate cuts for two-dimensional simulations. The geometric structure can be generated either directly from the layout by specifying constant layer thicknesses, or by a rigorous topography simulation [2]. For the creation of two-dimensional simulation grids the program Triangle [3] is used, for the three-dimensional case we perform a layer-based grid generation method [4]. As application example a polysilicon resistor pair is analyzed with the tools presented.

Keywords

Voltage Step Transmission Line Model Quadratic Shape Function Conjugate Gradient Solver Potential Distribution Function 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    R. Martins and S. Selberherr, “Layout Data in TCAD Frameworks,” in Modelling and Simulation, pp. 1122–1126, Society for Computer Simulation International, 1996.Google Scholar
  2. [2]
    E. Strasser and S. Selberherr, “Algorithms and Models for Cellular Based Topography Simulation,” IEEE Trans.Computer-Aided Design, vol. 14, no. 9, pp. 1104 – 1114, 1995.CrossRefGoogle Scholar
  3. [3]
    J. R. Shewchuk, “Triangle: Engineering a 2D Quality Mesh Generator and Delaunay Triangulator,” in First Workshop on Applied Computational Geometry, pp. 124 – 133, Association for Computing Machinery, May 1996.Google Scholar
  4. [4]
    P. Fleischmann, R. Sabelka, A. Stach, R. Strasser, and S. Selberherr, “Grid Generation for Three Dimensional Process and Device Simulation,” in International Conference on Simulation of Semiconductor Processes and Devices, pp. 161–166, Business Center for Academic Societies Japan, 1996.Google Scholar
  5. [5]
    W. Schroeder, K. Martin, B. Lorensen, L. Sobierajski-Avila, R. Avila, and C. C. Law, The Visualization Toolkit, An Object-Oriented Approach to 3D Graphics. Prentice Hall PTR/New Jersey, 1996.Google Scholar
  6. [6]
    R. Sabelka, K. Koyama, and S. Selberherr, “STAP—A Finite Element Simulator for Three-Dimensional Thermal Analysis of Interconnect Structures,” in Simulation in Industry—9th European Simulation Symposium, pp. 621–625. Oct. 1997.Google Scholar

Copyright information

© Springer-Verlag/Wien 1998

Authors and Affiliations

  • R. Sabelka
    • 1
  • R. Martins
    • 1
  • S. Selberherr
    • 1
  1. 1.Institute for MicroelectronicsTU ViennaViennaAustria

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