Abstract
A coupled fully three-dimensional process and device simulation of an advanced NMOS transistor using new 3D process simulation tools was performed. A POCKET doping resulting from large angle tilted implantation was included in the process flow. 3D effects originating from the non planar 3D mask have been analyzed. Simulation of the transfer characteristics shows a remarkable influence of 3D device and process features on electrical device behavior. A lower sensitivity to substrate bias has been observed in the 3D device compared to standard 2D simulation.
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References
M. Rodder, S. Aur, I.-C. Chen, “A Scaled 1.8 V, 0.18µm Gate Length CMOS Technology: Device Design and Reliability Considerations”, in: IEDM’95 Technical Digest 1995, pp. 415–418
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© 1998 Springer-Verlag/Wien
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Tietzel, K., Bourenkov, A., Lorenz, J. (1998). Coupled 3D Process and Device Simulation of Advanced MOSFETs. In: De Meyer, K., Biesemans, S. (eds) Simulation of Semiconductor Processes and Devices 1998. Springer, Vienna. https://doi.org/10.1007/978-3-7091-6827-1_64
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DOI: https://doi.org/10.1007/978-3-7091-6827-1_64
Publisher Name: Springer, Vienna
Print ISBN: 978-3-7091-7415-9
Online ISBN: 978-3-7091-6827-1
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