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Coupled 3D Process and Device Simulation of Advanced MOSFETs

  • K. Tietzel
  • A. Bourenkov
  • J. Lorenz
Conference paper

Abstract

A coupled fully three-dimensional process and device simulation of an advanced NMOS transistor using new 3D process simulation tools was performed. A POCKET doping resulting from large angle tilted implantation was included in the process flow. 3D effects originating from the non planar 3D mask have been analyzed. Simulation of the transfer characteristics shows a remarkable influence of 3D device and process features on electrical device behavior. A lower sensitivity to substrate bias has been observed in the 3D device compared to standard 2D simulation.

Keywords

Gate Oxide Substrate Bias Device Simulation Short Channel Effect Doping Distribution 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    M. Rodder, S. Aur, I.-C. Chen, “A Scaled 1.8 V, 0.18µm Gate Length CMOS Technology: Device Design and Reliability Considerations”, in: IEDM’95 Technical Digest 1995, pp. 415–418Google Scholar
  2. [2]
    J. Lorenz, K. Tietzel, A. Bourenkov, H. Ryssel, “Three-Dimensional Simulation of Ion Implantation” in: Proc. SISPAD’96, 1995, pp. 23–24Google Scholar

Copyright information

© Springer-Verlag/Wien 1998

Authors and Affiliations

  • K. Tietzel
    • 1
  • A. Bourenkov
    • 1
  • J. Lorenz
    • 1
  1. 1.Fraunhofer Institut für Integrierte Schaltungen Bereich BauelementetechnologieErlangenGermany

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