Effects of scaling and lattice heating on n-MOSFET performance via electrothermal Monte Carlo simulation
The technological advances which have enabled fabrication of devices ever deeper into the submicron regime have left many new and unexplored theoretical questions in their wake. In this study, we investigate the effect of self-heating on charge transport and oxide degradation in n-channel MOSFETs as a function of channel length and applied bias via the Monte Carlo and hydrodynamic methods. We demonstrate the increasing importance of self-heating with decreasing device dimension, and show that even moderate lattice heating can significantly suppress the high energy tail of the electron distribution function as well as influence the oxide degradation rate under normal device operation.
KeywordsLattice Temperature Electron Distribution Function Gate Current High Energy Tail Eyring Model
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- Daebin Yim, Hyunchul Kim, Doohun Song, Junho Baek, “Layout optimization of ESD protection TFO-NMOS by two-dimensional device simulation,” Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 1997, pp. 29–31.Google Scholar
- Steven H. Voldman, Stephen S. Furkay, James R. Slinkman, “Three- Dimensional Transient Electrothermal Simulation of Electrostatic Discharge Protection Circuits,” Electrical Overstress/ Electrostatic Discharge Symposium Proceedings, Las Vegas, Nevada, 1994, pp. 6.2.1–6.2.11.Google Scholar
- Y. Chen, S. N. Ekkanath Madathil, F. J. Clough, W. I. Milne, “The Influence of Lattice Temperature on SOI MOSFET’s Output Characteristics,” IEE Colloquium on “Physical Modelling of Semiconductor Devices,” April 1995, pp. 8/1–8/4.Google Scholar
- Hitoshi Yamaguchi, Hiroaki Himi, Shigeyuki Akita, Toshiyuki Morishita, “Analysis of Self-Heating in SOI High Voltage MOS Transistor,” IEICE Transactions on Electronics, E80-C, 1997, pp. 423–429Google Scholar