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A Methodology for Deep Sub-Quartermicron CMOS Technology Characterization

  • V. Palankovski
  • N. Belova*
  • T. Grasser
  • H. Puchner
  • S. Aronowitz
  • S. Selberherr

Abstract

We present a novel methodology for characterization of sub-quartermicron CMOS technologies. It involves process calibration, device calibration employing two-dimensional device simulation and automated Technology Computer Aided Design (TCAD) optimization, and, finally, transient mixed-mode device/circuit simulation. The proposed methodology was tested on 0.25 εm technology and applied to 0.13 εm technology in order to estimate ring oscillator speed. The simulation results show an excellent agreement with available experimental data.

Keywords

Gate Length Ring Oscillator Gate Delay Device Calibration PMOS Device 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Wien 2001

Authors and Affiliations

  • V. Palankovski
    • 1
  • N. Belova*
    • 1
  • T. Grasser
    • 1
  • H. Puchner
  • S. Aronowitz
    • 1
  • S. Selberherr
    • 1
  1. 1.Institute for MicroelectronicsTU Vienna Gusshausstrasse 27-29 A-1040 ViennaSanta ClaraAustriaUSA

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