Stress Modelling of Multi Level Interconnect Schemes For Future Deep Submicron Device Generations
Copper and low dielctric constantant (k) materials are poised to become the dominant interconnect scheme for integrated circuits for the future because of the low resistance and capacitance that they offer which can improve circuit performance by more than 30% over conventional interconnect schemes. This paper addresses the thermomechanical stresses in the Cu/Low k interconnect scheme through numerical simulation and identifies the locations of maximum stress in the structure with view to providing information on the impact that different dielectric materials have on the stress distribution in the interfaces between metals and dielectric layers.
KeywordsTitanium Nitride Copper Layer Finite Element Modelling Simulation Thermomechanical Stress Metal Barrier
Unable to display preview. Download preview PDF.
- C.G.M. DeOca M. Eng. Sc Thesis, National University of Ireand—Cork (NUIC) (2000)Google Scholar
- W.E.Beadle J.C.C.Tsai, R.D.Plumber. Quick Reference Manual For Silicon Integrated Circuit Technology, John Wiley&SOns New York 1985Google Scholar
- Swanson Analysis Systems, Inc. P.O.Box 65, Johnston Road Houston,PA 15324 ¡ª 0065 Ansys Users Manual.Google Scholar
- ANSYS Inc 2001 Inc. P.O.Box 65, Johnston Road Houston,PA 15342 ¡ª 1300 Ansys Workbook July 1996.Google Scholar
- E.M.Zielinsky,S. W.Russell„R.S.List,A.M. Wilson,C.Jin,K.J.Newton,J.P.Lu, W.Y.Hsu,V.0 ordasco. Proc. IEEE Hong Kong Electron Devices Meeting.1997 pp 936–938Google Scholar
- A. I. Sauter,, PhD Thesis, Leand Stanford Junior University, USA. Feb. 1991Google Scholar
- S.Foley PhD Thesis NUIC. Irl 2000Google Scholar