Abstract
In this paper we present a SPICE-compatible macro model based on three MOS transistors to describe split-gate non-volatile memory (NVM) cell characteristics for various sizes of the gap between the gates. The model has initially been developed based on simulated dc-IV-characteristics of reference cells (floating gate connected to control gate) and was verified later with measurements on reference as well as real floating gate cells.
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References
M. van Duuren et al., “Compact poly-CMP embedded flash memory cells for one or two bit storage,” in Proc. NVSMW, pp. 73-74, 2003.
S-P. Sim et al., “Parameter and coupling ratio extraction for SPICE-compatible macro modeling of source side injection flash cell”, in Proc. SISPAD, pp.356-359, 2001.
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© 2004 Springer-Verlag Wien
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Akil, N., van Langevelde, R., Goarin, P., van Duuren, M., Slotboom, M. (2004). SPICE-Compatible Macro Model for Split-Gate Compact NVM Cell with Various Gap Sizes. In: Wachutka, G., Schrag, G. (eds) Simulation of Semiconductor Processes and Devices 2004. Springer, Vienna. https://doi.org/10.1007/978-3-7091-0624-2_61
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DOI: https://doi.org/10.1007/978-3-7091-0624-2_61
Publisher Name: Springer, Vienna
Print ISBN: 978-3-7091-7212-4
Online ISBN: 978-3-7091-0624-2
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