Abstract
Coupled three-dimensional process and device simulations have been applied to study effects limiting the performance of FinFETs, a novel CMOS transistors suggested to overcome the limitations of conventional CMOS for gate lengths at 50 nm and below.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
D. Hisamoto, Wen-Chin-Lee, J. Kedzierski et al., A folded-channel MOSFET for deepsub-tenth micron era, in: IEDM Digest 1998, IEEE, Piscataway, NJ, 1998, p. 1032.
A. Burenkov, J. Lorenz, Corner effect in double and triple gate FinFETs, in: Proc. ESSDERC 2003. Eds.: J. Franca and P. Freitas, Estoril, Portugal, 2003, p. 135.
E. Bär, J. Lorenz, H. Ryssel, Three-dimensional simulation of layer deposition, Microelectronics Journal, 29 (1998) 799.
O. Lenhart, E. Bär, Three-dimensional triangle-based simulation of etching processes and applications, IEICE Trans. Electron., EC86-C (2003) 427.
A. Burenkov, K. Tietzel, A. Hös singer, J. Lorenz, H. Ryssel, S. Selberherr, A computationally efficient method for three-dimensional simulation of ion implantation, IEICE Trans. Electron., E83-C (1999) 1259.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Wien
About this paper
Cite this paper
Burenkov, A., Lorenz, J. (2004). 3D Simulation of Process Effects Limiting FinFET Performance and Scalability. In: Wachutka, G., Schrag, G. (eds) Simulation of Semiconductor Processes and Devices 2004. Springer, Vienna. https://doi.org/10.1007/978-3-7091-0624-2_30
Download citation
DOI: https://doi.org/10.1007/978-3-7091-0624-2_30
Publisher Name: Springer, Vienna
Print ISBN: 978-3-7091-7212-4
Online ISBN: 978-3-7091-0624-2
eBook Packages: Springer Book Archive