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Scaling, Power Consumption, and Mobility Enhancement Techniques

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Strain-Induced Effects in Advanced MOSFETs

Part of the book series: Computational Microelectronics ((COMPUTATIONAL))

Abstract

The power dissipation of a CMOS circuit consists of the dynamic (due to switching) and the static contribution in the off-state and can be written as (68)

$$P ={ \sum\nolimits }_{i}{\alpha }_{i}{C}_{i}{V }_{{\it { DD}}}^{2}f + {I}_{ {\it { OFF}}}{V }_{{\it { DD}}},$$
(2.1)

where 0 < α i < 1 is the “switching activity factor” of the ith circuit block, C i is the total effective capacitance including that of all the interconnects and input capacitance of transistors, f is the clock frequency, and I OFF is the total current in the off-state of all the transistors biased by the power supply voltage V DD .

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References

  1. Andrieu, F., Ernst, T., Faynot, O., Rozeau, O., Bogumilowicz, Y., Hartmann, J.M., Brevard, L., Toffoli, A., Lafond, D., Ghyselen, B.: Performance and physics of sub-50 nm strained Si on Si1 − x Ge x on insulator (SGOI) nMOSFETs. Solid State Electron. 50, 566–572 (2006)

    Article  Google Scholar 

  2. Ang, K.W., Chui, K.J., Bliznetsov, V., Du, A., Balasubramanian, N., Li, M.F., Samudra, G., Yeo, Y.C.: Enhanced performance in 50 nm n-MOSFETs with silicon-carbon source/drain regions. In: Int. Electron Devices Meeting, pp. 1069–1071 (2004)

    Google Scholar 

  3. Ang, K.W., Chui, K.J., Bliznetsov, V., Tung, C.H., Du, A., Balasubramanian, N., Samudra, G., Li, M.F., Yeo, Y.C.: Lattice strain analysis of transistor structures with silicon–germanium and silicon–carbon source/drain stressors. Appl. Phys. Lett. 86(9), 093102 (2005)

    Article  Google Scholar 

  4. Arghavani, R., Xia, L., Saad, H., Balseanu, M., Karunasiri, G., Mascarenhas, A., Thompson, S.E.: A reliable and manufacturable method to induce a stress of > 1 Gpa on a p-channel MOSFET in high volume manufacturing. IEEE Electron Device Lett. 27(2), 114–116 (2006)

    Article  Google Scholar 

  5. Auth, C., Cappellani, A., Chun, J.S., Dalis, A., Davis, A., Ghani, T., Glass, G., Glassman, T., Harper, M., Hattendorf, M., Hentges, P., Jaloviar, S., Joshi, S., Klaus, J., Kuhn, K., Lavric, D., Lu, M., Mariappan, H., Mistry, K., Norris, B., Rahhal-orabi, N., Ranade, P., Sandford, J., Shifren, L., Souw, V., Tone, K., Tambwe, F., Thompson, A., Towner, D., Troeger, T., Vandervoorn, P., Wallace, C., Wiedemer, J., Wiegand, C.: 45 nm high-k + metal gate strain-enhanced transistors. In: VLSI Technology, 2008 Symposium on, pp. 128–129 (2008)

    Google Scholar 

  6. Bai, P., Auth, C., Balakrishnan, S., Bost, M., Brain, R., Chikarmane, V., Heussner, R., Hussein, M., Hwang, J., Ingerly, D., James, R., Jeong, J., Kenyon, C., Lee, E., Lee, S.H., Lindert, N., Liu, M., Ma, Z., Marieb, T., Murthy, A., Nagisetty, R., Natarajan, S., Neirynck, J., Ott, A., Parker, C., Sebastian, J., Shaheed, R., Sivakumar, S., Steigerwald, J., Tyagi, S., Weber, C., Woolery, B., Yeoh, A., Zhang, K., Bohr, M.: A 65 nm logic technology featuring 35 nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57μm 2 SRAM cell. In: Intl. Electron Devices Meeting, pp. 657–660 (2004)

    Google Scholar 

  7. Bardeen, J., Shockley, W.: Deformation potentials and mobilities in non-polar crystals. Phys. Rev. 80(1), 72–80 (1950)

    Article  MathSciNet  MATH  Google Scholar 

  8. Bir, G.L., Pikus, G.E.: Symmetry and strain-induced effects in semiconductors. Willey, New York - Toronto (1974)

    Google Scholar 

  9. Chan, V., Rengarajan, R., Rovedo, N., Jin, W., Hook, T., Nguyen, P., Chen, J., Nowak, E., Chen, X.D., Lea, D., Chakravarti, A., Ku, V., Yang, S., Steegen, A., Baiocco, C., Shafer, P., Ng, H., Huang, S.F., Wann, C.: High speed 45 nm gate length CMOSFETs integrated into a 90 nm bulk technology incorporating strain engineering. In: Intl. Electron Devices Meeting, pp. 77–80 (2003)

    Google Scholar 

  10. Chan, V., Rim, K., Ieong, M., Yang, S., Malik, R., Teh, Y.W., Yang, M., Ouyang, Q.C.: Strain for CMOS performance improvement. pp. 667 – 674 (2005)

    Google Scholar 

  11. Chen, C.H., Lee, T., Hou, T., Chen, C., Chen, C., Hsu, J., Cheng, K., Chiu, Y., Tao, H., Jin, Y., Diaz, C., Chen, S., Liang, M.S.: Stress memorization technique (smt) by selectively strained-nitride capping for sub-65 nm high-performance strained-si device application. In: VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on, pp. 56–57 (2004). DOI 10.1109/VLSIT.2004.1345390

    Google Scholar 

  12. Chidambaram, P.R., Bowen, C., Chakravarthi, S., Machala, C., Wise, R.: Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing. IEEE Trans. Electron Devices 53(5), 944–964 (2006)

    Article  Google Scholar 

  13. Chui, C.O., Ramanathan, S., Triplett, B.B., McIntyre, P.C., Saraswat, K.C.: Ultrathin high-k gate dielectric technology for germanium MOS applications. In: Proc. Device Research Conf., pp. 191–192 (2002)

    Google Scholar 

  14. Chui, K.J., Ang, K.W., Balasubramanian, N., Li, M.F., Samudra, G.S., Yeo, Y.C.: n-MOSFET with silicon–carbon source/drain for enhancement of carrier transport. IEEE Trans. Electron Devices 54, 249–256 (2007)

    Article  Google Scholar 

  15. Datta, S., Dewey, G., Doczy, M., Doyle, B., Jin, B., Kavalieros, J., Kotlyar, R., Metz, M., Zelick, N., Chau, R.: High mobility Si/SiGe strained channel MOS transistors with HfO2/TiN gate stack. In: Intl. Electron Devices Meeting, pp. 28.1.1–28.1.4 (2003)

    Google Scholar 

  16. Donaton, R.A., Chidambarrao, D., Johnson, J., Chang, P., Liu, Y., Henson, W.K., Holt, J., Li, X., Li, J., Domenicucci, A., Madan, A., Rim, K., Wann, C.: Design and fabrication of MOSFETs with a reverse embedded sige (rev. e-SiGe) structure. In: Intl. Electron Devices Meeting, pp. 1–4 (2006)

    Google Scholar 

  17. Eneman, S., Verheyen, P., Rooyackers, R., Nouri, F., Washington, L., Degraeve, R., Kaczer, B., Moroz, V., De Keersgieter, A., Schreutelkamp, R., Kawaguchi, M., Kim, Y., Samoilov, A., Smith, L., Absil, P.P., De Meyer, K., Jurczak, M., Biesemans, S.: Layout impact on the performance of a locally strained PMOSFET. In: Proc. Symposium on VLSI Technology, pp. 22–23 (2005)

    Google Scholar 

  18. Fitzgerald, E., Xie, Y., Green, M., Brasen, D., Kortan, A., Michel, J., Mii, Y., Weir, B.: Totally relaxed Ge x Si1 − x layers with low threading dislocation densities grown on Si substrates. Appl. Phys. Lett. 59(7), 811–813 (1991)

    Article  Google Scholar 

  19. Gannavaram, S., Pesovic, N., Ozturk, C.: Low temperature (800 ∘ C) recessed junction selective silicon-germanium source/drain technology for sub-70 nm CMOS. In: Intl. Electron Devices Meeting, pp. 437–440 (2000). DOI 10.1109/IEDM.2000.904350

    Google Scholar 

  20. Ghani, T., Armstrong, M., Auth, C., Bost, M., Charvat, P., Glass, G., Hoffmann, T., Johnson, K., Kenyon, C., Klaus, J., McIntyre, B., Mistry, K., Murthy, A., Sandford, J., Silberstein, M., Sivakumar, S., Smith, P., Zawadzki, K., Thompson, S., Bohr, M.: A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors. In: Intl. Electron Devices Meeting, pp. 11.6.1–11.6.3 (2003)

    Google Scholar 

  21. Ghyselen, B., Hartmann, J.M., Ernst, T., Aulnette, C., Osternaud, B., Bogumilowicz, Y., Abbadie, A., Besson, P., Rayssac, O., Tiberj, A.: Engineering strained silicon on insulator wafers with the smart cut technology. Solid State Electron. 48, 1285–1296 (2004)

    Article  Google Scholar 

  22. Gusev, E.P., Narayanan, V., Frank, M.M.: Advanced high-k dielectric stacks with polysi and metal gates: Recent progress and current challenges. IBM J. Res. Dev. 50(4–5), 387–410 (2006)

    Article  Google Scholar 

  23. Hall, H.H., Bardeen, J., Pearson, G.L.: The effects of pressure and temperature on the resistance of p − n junctions in germanium. Phys. Rev. 84(1), 129–132 (1951). DOI 10.1103/PhysRev. 84.129

    Article  Google Scholar 

  24. Hensel, J.C., Feher, G.: Cyclotron resonance experiments in uniaxially stressed silicon: Valence band inverse mass parameters and deformation potentials. Phys. Rev. 129(3), 1041–1062 (1963). DOI 10.1103/PhysRev.129.1041

    Article  MATH  Google Scholar 

  25. Hensel, J.C., Hasegawa, H., Nakayama, M.: Cyclotron resonance in uniaxially stressed silicon. II. Nature of the covalent bond. Phys. Rev. 138(1A), A225–A238 (1965)

    Google Scholar 

  26. Herring, C., Vogt, E.: Transport and deformation-potential theory for many-valley semiconductors with anisotropic scattering. Phys. Rev. 101(3), 944–961 (1956)

    Article  MATH  Google Scholar 

  27. Horstmann, M., Wei, A., Kammler, T., Höntschel, J., Bierstedt, H., Feudel, T., Frohberg, K., Gerhardt, M., Hellmich, A., Hempel, K., Hohage, J., Javorka, P., Klais, J., Koerner, G., Lenski, M., Neu, A., Otterbach, R., Press, P., Reichel, C., Trentsch, M., Trui, B., Salz, H., Schaller, M., Engelmann, H.J., Herzog, O., Ruelke, H., Hübler, P., Stephan, R., Greenlaw, D., Raab, M., Kepler, N.: Integration and optimization of embedded-SiGe, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies. In: Intl. Electron Devices Meeting, pp. 233–236 (2005)

    Google Scholar 

  28. Hudait, M., Chau, R.: Integrating III-V on silicon for future nanoelectronics. In: Compound Semiconductor Integrated Circuits Symposium, 2008. CSICS ’08. IEEE, pp. 1–2 (2008)

    Google Scholar 

  29. Hudait, M., Dewey, G., Datta, S., Fastenau, J., Kavalieros, J., Liu, W., Lubyshev, D., Pillarisetty, R., Rachmady, W., Radosavljevic, M., Rakshit, T., Chau, R.: Heterogeneous integration of enhancement mode In0. 7Ga0. 3As quantum well transistor on silicon substrate using thin (less than 2 μm) composite buffer architecture for high-speed and low-voltage (0.5V) logic applications. In: Intl. Electron Devices Meeting, pp. 625–628 (2007)

    Google Scholar 

  30. Irisawa, T., Numata, T., Tezuka, T., Usuda, K., Nakaharai, S., Hirashita, N., Sugiyama, N., Toyoda, E., Takagi, S.: High performance multi-gate pMOSFET using uniaxially-strained SGOI channels. In: Intl. Electron Devices Meeting, pp. 709–712 (2005)

    Google Scholar 

  31. Irisawa, T., Numata, T., Tezuka, T., Usuda, K., Sugiyama, N., Takagi, S.I.: Device design and electron transport properties of uniaxially strained-SOI tri-gate nMOSFETs. IEEE Trans. Electron Devices 55(2), 649–654 (2008)

    Article  Google Scholar 

  32. Irisawa, T., Okano, K., Horiuchi, T., Itokawa, H., Mizushima, I., Usuda, K., Tezuka, T., Sugiyama, N., Takagi, S.I.: Electron mobility and short-channel device characteristics of SOI FinFETs with uniaxially strained (110) channels. IEEE Trans. Electron Devices 56(8), 1651–1658 (2009)

    Article  Google Scholar 

  33. Ito, S., Namba, H., Yamaguchi, K., Hirata, T., Ando, K., Koyama, S., Kuroki, S., Ikezawa, N., Suzuki, T., Saitoh, T., Horiuchi, T.: Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design. In: Intl. Electron Devices Meeting, pp. 247–251 (2000)

    Google Scholar 

  34. James, D.: 2004 - the year of 90 nm: a review of 90 nm devices. In: Advanced Semiconductor Manufacturing Conference and Workshop, 2005 IEEE/SEMI, pp. 72–76 (2005)

    Google Scholar 

  35. Jan, C.H., Bai, P., Choi, J., Curello, G., Jacobs, S., Jeong, J., Johnson, K., Jones, D., Klopcic, S., Lin, J., Lindert, N., Lio, A., Natarajan, S., Neirynck, J., Packan, P., Park, J., Post, I., Patel, M., Ramey, S., Reese, P., Rockford, L., Roskowski, A., Sacks, G., Turkot, B., Wang, Y., Wei, L., Yip, J., Young, I., Zhang, K., Zhang, Y., Bohr, M., Holt, B.: A 65 nm ultra low power logic platform technology using uni-axial strained silicon transistors. In: Intl. Electron Devices Meeting, pp. 60–63 (2005)

    Google Scholar 

  36. Khamankar, R., Bu, H., Bowen, C., Chakravarthi, S., Chidambaram, P.R., Bevan, M., Krishnan, A., Niimi, H., Smith, B., Blatchford, J., Hornung, B., Lu, J.P., Nicollian, P., Kirkpatrick, B., Miles, D., Hewson, M., Farber, D., Hall, L., Alshareef, H., Varghese, A., Gurba, A., Ukraintsev, V., Rathsack, B., DeLoach, J., Tran, J., Kaneshige, C., Somervell, M., Aur, S., Machala, C., Grider, T.: An enhanced 90 nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes. In: Proc. Symposium on VLSI Technology, pp. 162–163 (2004)

    Google Scholar 

  37. Komoda, T., Oishi, A., Sanuki, T., Kasai, K., Yoshimura, H., Ohno, K., Iwai, A., Saito, M., Matsuoka, F., Nagashima, N., Noguchi, T.: Mobility improvement for 45 nm node by combination of optimized stress and channel orientation design. In: Intl. Electron Devices Meeting, pp. 217–220 (2004)

    Google Scholar 

  38. Lee, M.L., Fitzgerald, E.A., Bulsara, M.T., Currie, M.T., Lochtefeld, A.: Strained si, sige, and ge channels for high-mobility metal-oxide-semiconductor field-effect transistors. J. Appl. Phys. 97(1), 011101 (2005)

    Article  Google Scholar 

  39. Lim, J.S., Thompson, S.E., Fossum, J.G.: Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs. IEEE Electron Device Lett. 25, 731–733 (2004)

    Article  Google Scholar 

  40. Luttinger, J.M., Kohn, W.: Motion of electrons and holes in perturbed periodic fields. Phys. Rev. 97(4), 869–883 (1955)

    Article  MATH  Google Scholar 

  41. Matsumoto, T., Maeda, S., Dang, H., Uchida, T., Ota, K., Hirano, Y., Sayama, H., Iwamatsu, T., Ipposhi, T., Oda, H., Maegawa, S., Inoue, Y., Nishmura, T.: Novel SOI wafer engineering using low stress and high mobility CMOSFET with ⟨100⟩ channel for embedded RF/analog applications. In: Intl. Electron Devices Meeting, pp. 663–666 (2002)

    Google Scholar 

  42. Mayuzumi, S., Yamakawa, S., Kosemura, D., Takei, M., Nagata, K., Akamatsu, H., Aamari, K., Tateshita, Y., Wakabayashi, H., Tsukamoto, M., Ohno, T., Saitoh, M., Ogura, A., Nagashima, N.: Comparative study between si (110) and (100) substrates on mobility and velocity enhancements for short-channel highly-strained pfets. In: VLSI Technology, 2009 Symposium on, pp. 14–15 (2006)

    Google Scholar 

  43. Mistry, K., Allen, C., Auth, C., Beattie, B., Bergstrom, D., Bost, M., Brazier, M., Buehler, M., Cappellani, A., Chau, R., Choi, C.H., Ding, G., Fischer, K., Ghani, T., Grover, R., Han, W., Hanken, D., Hattendorf, M., He, J., Hicks, J., Huessner, R., Ingerly, D., Jain, P., James, R., Jong, L., Joshi, S., Kenyon, C., Kuhn, K., Lee, K., Liu, H., Maiz, J., McIntyre, B., Moon, P., Neirynck, J., Pae, S., Parker, C., Parsons, D., Prasad, C., Pipes, L., Prince, M., Ranade, P., Reynolds, T., Sandford, J., Shifren, L., Sebastian, J., Seiple, J., Simon, D., Sivakumar, S., Smith, P., Thomas, C., Troeger, T., Vandervoorn, P., Williams, S., Zawadzki, K.: A 45 nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging. In: Intl. Electron Devices Meeting, pp. 247–250 (2007)

    Google Scholar 

  44. Natarajan, S., Armstrong, K., Bost, M., Brain, R., Brazier, M., Chang, C.H., Chikarmane, V., Childs, M., Deshpande, H., Dev, K., Ding, G., Ghani, T., Golonzka, O., Han, W., He, J., Heussner, R., James, R., Jin, I., Kenyon, C., Klopcic, S., Lee, S.H., Liu, M., Lodha, S., McFadden, B., Murthy, A., Neiberg, L., Neirynck, J., Packan, P., Pae, S., Parker, C., Pelto, C., Pipes, L., Sebastian, J., Seiple, J., Sell, B., Sivakumar, S., Song, B., Tone, K., Troeger, T., Weber, C., Yang, M., Yeoh, A., Zhang, K.: A 32 nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array. In: Intl. Electron Devices Meeting, pp. 941–943 (2008)

    Google Scholar 

  45. Nayak, D., Goto, K., Yutani, A., Murota, J., Shiraki, Y.: High-mobility strained-Si PMOSFET’s. IEEE Trans. Electron Devices 43(10), 1709–1716 (1996)

    Article  Google Scholar 

  46. Nayak, D., Woo, J., Park, J., Wang, K., MacWilliams, K.: High-mobility p-channel metal-oxide-semiconductor field-effect-transistor on strained Si. Jpn. J. Appl. Phys. 33, 2412–2414 (1994)

    Article  Google Scholar 

  47. Oh, J., Ok, I., Kang, C.Y., Jamil, M., Lee, S.H., Loh, W.Y., Huang, J., Sassman, B., Smith, L., Parthasarathy, S., Coss, B., Choi, W.H., Lee, H.D., Cho, M., Banerjee, S., Majhi, P., Kirsch, P., Tseng, H.H., Jammy, R.: Mechanisms for low on-state current of Ge (SiGe) nMOSFETs: A comparative study on gate stack, resistance, and orientation-dependent effective masses. In: VLSI Technology, 2009 Symposium on, pp. 238–239 (2006)

    Google Scholar 

  48. Ota, K., Sugihara, K., Sayama, H., Uchida, T., Oda, H., Eimori, T., Morimoto, H., Inoue, Y.: Novel locally strained channel technique for high performance 55 nm CMOS. In: Intl. Electron Devices Meeting, pp. 27–30 (2002)

    Google Scholar 

  49. Ouyang, Q., Yang, M., Holt, J., Panda, S., Chen, H., Utomo, H., Fischetti, M., Rovedo, N., Li, J., Klymko, N., Wildman, H., Kanarsky, T., Costrini, G., Fried, D., Bryant, A., Ott, J., Ieong, M., Sung, C.: Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates. In: Proc. Symposium on VLSI Technology, pp. 28–29 (2005)

    Google Scholar 

  50. Packan, P., Akbar, S., Armstrong, M., Bergstrom, D., Brazier, M., Deshpande, H., Dev, K., Ding, G., Ghani, T., Golonzka, O., Han, W., He, J., Heussner, R., James, R., Jopling, J., Kenyon, C., Lee, S.H., Liu, M., Lodha, S., Mattis, B., Murthy, A., Neiberg, L., Neirynck, J., Pae, S., Parker, C., Pipes, L., Sebastian, J., Seiple, J., Sell, B., Sharma, A., Sivakumar, S., Song, B., St. Amour, A., Tone, K., Troeger, T., Weber, C., Zhang, K., Luo, Y., Natarajan, S.: High performance 32 nm logic technology featuring 2nd generation high-k + metal gate transistors. pp. 1 –4 (2009)

    Google Scholar 

  51. Radosavljevic, M., Ashley, T., Andreev, A., Coomber, S., Dewey, G., Emeny, M., Fearn, M., Hayes, D., Hilton, K., Hudait, M., Jefferies, R., Martin, T., Pillarisetty, R., Rachmady, W., Rakshit, T., Smith, S., Uren, M., Wallis, D., Wilding, P., Chau, R.: High-performance 40 nm gate length insb p-channel compressively strained quantum well field effect transistors for low-power (v CC = 0. 5V) logic applications. In: Intl. Electron Devices Meeting, pp. 1–4 (2008)

    Google Scholar 

  52. Radosavljevic, M., Chu-Kung, B., Corcoran, S., Dewey, G., Hudait, M., Fastenau, J., Kavalieros, J., Liu, W., Lubyshev, D., Metz, M., Millard, K., Mukherjee, N., Rachmady, W., Shah, U., Chau, R.: Advanced high-k gate dielectric for high-performance short-channel in0.7ga0.3as quantum well field effect transistors on silicon substrate for low power logic applications. In: Intl. Electron Devices Meeting, pp. 1 –4 (2009)

    Google Scholar 

  53. Rim, K., Chan, K., Shi, L., Boyd, D., Ott, J., Klymko, N., Cardone, F., Tai, L., Koester, S., Cobb, M., Canaperi, D., To, B., Duch, E., Babich, I., Carruthers, R., Saunders, P., Walker, G., Zhang, Y., Steen, M., Ieong, M.: Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs. In: Intl. Electron Devices Meeting, pp. 49–52 (2003)

    Google Scholar 

  54. Rim, K., Chu, J., Chen, H., Jenkins, K., Kanarsky, T., Lee, K., Mocuta, A., Zhu, H., Roy, R., Newbury, J., Ott, J., Petrarca, K., Mooney, P., Lacey, D., Koester, S., Chan, K., Boyd, D., Ieong, M., Wong, H.: Characteristics and device design of sub-100 nm strained Si n- and p-MOSFETs. In: Proc. Symposium on VLSI Technology, pp. 98–99 (2002)

    Google Scholar 

  55. Rim, K., Hoyt, J., Gibbons, J.: Transconductance enhancement in deep submicron strained Si n-MOSFETs. In: Intl. Electron Devices Meeting, pp. 707–710 (1998)

    Google Scholar 

  56. Rim, K., Welser, J., Hoyt, J., Gibbons, J.: Enhanced hole mobilities in surface-channel strained-Si p-MOSFETs. In: Intl. Electron Devices Meeting, pp. 517–520 (1995)

    Google Scholar 

  57. Rupp, K., Selberherr, S.: The economic limit to Moore’s law. Proc. of the IEEE 98(3), 351–353 (2010)

    Article  Google Scholar 

  58. Sadaka, M., Thean, A., Barr, A., Tekleab, D., Kalpat, S., White, T.: Fabrication and operation of sub-50 nm strained-Si on Si1 − x Ge x on insulator (SGOI) CMOSFETs. In: Proc. IEEE International SOI Conference, pp. 209–211 (2004)

    Google Scholar 

  59. Scott, G., Lutze, J., Rubin, M., Nouri, F., Manley, M.: NMOS drive current reduction caused by transistor layout and trench isolation induced stress. In: Intl. Electron Devices Meeting, pp. 827–830 (1999)

    Google Scholar 

  60. Sheraw, C., Yang, M., Fried, D., Costrini, G., Kanarsky, T., Lee, W., Chan, V., Fischetti, M., Holt, J., et al.: Dual stress liner enhancement in hybrid orientation technology. In: Proc. Symposium on VLSI Technology, pp. 12–13 (2005)

    Google Scholar 

  61. Shimizu, A., Hachimine, K., Ohki, N., Ohta, H., Koguchi, M., Nonaka, Y., Sato, H., Ootsuka, F.: Local mechanical-stress control (LMC): A new technique for CMOS-performance enhancement. In: Intl. Electron Devices Meeting, pp. 433–436 (2001)

    Google Scholar 

  62. Sleight, J., Lauer, I., Dokumaci, O., Fried, D., Guo, D., Haran, B., Narasimha, S., Sheraw, C., Singh, D., Steigerwalt, M., Wang, X., Oldiges, P., Sadana, D., Sung, C., Haensch, W., Khare, M.: Challenges and opportunities for high performance 32 nm CMOS technology. In: Intl. Electron Devices Meeting, pp. 697–700 (2006)

    Google Scholar 

  63. Smith, C.S.: Piezoresistance effect in germanium and silicon. Phys. Rev. 94(1), 42–49 (1954)

    Article  Google Scholar 

  64. Steegen, A., Mo, R., Mann, R., Sun, M.C., Eller, M., Leake, G., Vietzke, D., Tilke, A., Guarin, F., Fischer, A., Pompl, T., Massey, G., Vayshenker, A., Tan, W., Ebert, A., Lin, W., Gao, W., Lian, J., Kim, J.P., Wrschka, P., Yang, J.H., Ajmera, A., Knoefler, R., Teh, Y.W., Jamin, F., Park, J., Hooper, K., Griffin, C., Nguyen, P., Klee, V., Ku, V., Baiocco, C., Johnson, G., Tai, L., Benedict, J., Scheer, S., Zhuang, H., Ramanchandran, V., Matusiewicz, G., Lin, Y.H., Siew, Y., Zhang, F., Leong, L., Liew, S., Park, K., Lee, K.W., Hong, D., Choi, S.M., Kaltalioglu, E., Kim, S., Naujok, M., Sherony, M., Cowley, A., Thomas, A., Sudijohno, J., Schiml, T., Ku, J.H., Yang, I.: 65 nm CMOS technology for low power applications. In: Intl. Electron Devices Meeting, pp. 64–67 (2005)

    Google Scholar 

  65. Steegen, A., Stucchi, M., Lauwers, A., Maex, K.: Silicide induced pattern density and orientation dependent transconductance in MOS transistors. In: Intl. Electron Devices Meeting, pp. 497–500 (1999)

    Google Scholar 

  66. Sun, G., Sun, Y., Nishida, T., Thompson, S.E.: Hole mobility in silicon inversion layers: Stress and surface orientation. J. Appl. Phys. 102(8), 084501 (2007)

    Article  Google Scholar 

  67. Suthram, S., Hussain, M.M., Harris, H.R., Smith, C., Tseng, H.H., Jammy, R., Thompson, S.E.: Comparison of Uniaxial Wafer Bending and Contact-Etch-Stop-Liner Stress Induced Performance Enhancement on Double-Gate FinFETs. IEEE Electron Device Lett. 29, 480–482 (2008)

    Article  Google Scholar 

  68. Sverdlov, V.A., Walls, T.J., Likharev, K.K.: Nanoscale silicon MOSFETs: A theoretical study. IEEE Trans. Electron Devices 50(9), 1926–1933 (2003)

    Article  Google Scholar 

  69. Thompson, S., Sun, G., Wu, K., Lim, J., Nishida, T.: Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs. In: Intl. Electron Devices Meeting, pp. 221–224 (2004)

    Google Scholar 

  70. Thompson, S.E., Armstrong, M., Auth, C., Cea, S., Chau, R., Glass, G., Hoffmann, T., Klaus, J., Ma, Z., McIntyre, B., Murthy, A., Obradovic, B., Shifren, L., Sivakumar, S., Tyagi, S., Ghani, T., Mistry, K., Bohr, M., El-Mansy, Y.: A logic nanotechnology featuring strained-silicon. IEEE Electron Device Lett. 25(4), 191–193 (2004)

    Article  Google Scholar 

  71. Thompson, S.E., Suthram, S., Sun, Y., Sun, G., Parthasarathy, S., Chu, M., Nishida, T.: Future of strained Si/semiconductors in nanoscale MOSFETs. In: Intl. Electron Devices Meeting, pp. 681–684 (2006)

    Google Scholar 

  72. Uchida, K., Krishnamohan, T., Saraswat, K.C., Nishi, Y.: Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime. In: Intl. Electron Devices Meeting, pp. 129–132 (2005)

    Google Scholar 

  73. Ungersboeck, E., Dhar, S., Karlowatz, G., Sverdlov, V., Kosina, H., Selberherr, S.: The effect of general strain on band structure and electron mobility of silicon. IEEE Trans. Electron Devices 54(9), 2183–2190 (2007)

    Article  Google Scholar 

  74. Uppal, S., Bollani, M., Willoughby, A., Bonar, J., Morris, R., Dowsett, M.: Diffusion of ion-implanted boron in high Ge content SiGe alloys. In: Electrocemical Society Proc., vol. 07, pp. 159–165 (2004)

    Google Scholar 

  75. Wang, J., Lundstrom, M.: Ballistic transport in high electron mobility transistors. IEEE Trans. Electron Devices 50(7), 1604–1609 (2003)

    Article  Google Scholar 

  76. Washington, L., Nouri, F., Thirupapuliyur, S., Eneman, G., Verheyen, P., Moroz, V., Smith, L., Xiaopeng, X., Kawaguchi, M., Huang, T., Ahmed, K., Balseanu, M., Li-Qun, X., Shen, M., Kim, Y., Rooyackers, R., Meyer, K.D., Schreutelkamp, R.: pMOSFET with 200% mobility enhancement induced by multiple stressors. IEEE Electron Device Lett. 27(6), 511–513 (2006)

    Article  Google Scholar 

  77. Welser, J., Hoyt, J., Gibbons, J.: NMOS and PMOS transistors fabricated in strained silicon/relaxed silicon-germanium structures. In: Intl. Electron Devices Meeting, pp. 1000–1002 (1992)

    Google Scholar 

  78. Welser, J., Hoyt, J., Gibbons, J.: Electron mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors. IEEE Electron Device Lett. 15(3), 100–102 (1994)

    Article  Google Scholar 

  79. Xiang, Q., Goo, J.S., Pan, J., Yu, B., Ahmed, S., Zhang, J., Lin, M.R.: Strained silicon nmos with nickel-silicide metal gate. In: VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on, pp. 101–102 (2003)

    Google Scholar 

  80. Yang, H.S., Malik, R., Narasimha, S., Li, Y., Divakaruni, R., Agnello, P., Allen, S., Antreasyan, A., Arnold, J.C., Bandy, K., Belyansky, M., Bonnoit, A., Bronner, G., Chan, V., Chen, X., Chen, Z., Chidambarrao, D., Chou, A., Clark, W., Crowder, S.W., Engel, B., Harifuchi, H., Huang, S.F., Jagannathan, R., Jamin, F.F., Kohyama, Y., Kuroda, H., Lai, C.W., Lee, H.K., Lee, W.H., Lim, E.H., Lai, W., Mallikarjunan, A., Matsumoto, K., McKnight, A., Nayak, J., Ng, H.Y., Panda, S., Rengarajan, R., Steigerwalt, M., Subbanna, S., Subramanian, K., Sudijono, J., Sudo, G., Sun, S.P., Tessier, B., Toyoshima, Y., Tran, P., Wise, R., Wong, R., Yang, I.Y., Wann, C.H., Su, L.T., Horstmann, M., Feudel, T., Wei, A., Frohberg, K., Burbach, G., Gerhardt, M., Lenski, M., Stephan, R., Wieczorek, K., Schaller, M., Salz, H., Hohage, J., Ruelke, H., Klais, J., Huebler, P., Luning, S., van Bentum, R., Grasshoff, G., Schwan, C., Ehrichs, E., Goad, S., Buller, J., Krishnan, S., Greenlaw, D., Raab, M., Kepler, N.: Dual stress liner for high performance sub-45 nm gate length SOI CMOS manufacturing. In: Intl. Electron Devices Meeting, pp. 1075–1077 (2004)

    Google Scholar 

  81. Yang, J.W., Fossum, J.G., Workman, G.O., Huang, C.L.: A physical model for gate-to-body tunneling current and its effects on floating-body PD/SOI CMOS devices and circuits. Solid State Electron. 48(2), 259–270 (2004)

    Article  Google Scholar 

  82. Yang, M., Chan, V., Chan, K., Shi, L., Fried, D., Stathis, J., et al.: Hybrid-orientation technology (HOT): Opportunities and challenges. IEEE Trans. Electron Devices 53, 965–978 (2006)

    Article  Google Scholar 

  83. Yokoyama, M., Yasuda, T., Takagi, H., Yamada, H., Fukuhara, N., Hata, M., Sugiyama, M., Nakano, Y., Takenaka, M., Takagi, S.: High mobility metal S/D IIIV-On-Insulator MOSFETs on a Si substrate using direct wafer bonding. In: VLSI Technology, 2009 Symposium on, pp. 242–243 (2006)

    Google Scholar 

  84. Yu, B., Wang, H., Milic, O., Xiang, Q., Wang, W., An, J., Lin, M.R.: 50 nm gate-length CMOS transistor with super-halo: design, process, and reliability. In: Intl. Electron Devices Meeting, pp. 653–656 (1999)

    Google Scholar 

  85. Zhang, D., Nguyen, B., White, T., Goolsby, B., et al.: Embedded SiGe S/D PMOS on thin body SOI substrate with drive current enhancement. In: Proc. Symposium on VLSI Technology, pp. 26–27 (2005)

    Google Scholar 

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    Viktor Sverdlov

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Sverdlov, V. (2011). Scaling, Power Consumption, and Mobility Enhancement Techniques. In: Strain-Induced Effects in Advanced MOSFETs. Computational Microelectronics. Springer, Vienna. https://doi.org/10.1007/978-3-7091-0382-1_2

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