Abstract
The intensive research and development (R&D) directed toward DRAMs has rapidly increased memory-chip capacity by more than six orders (1 Kb to 4 Gb) at the R&D level over the past 30 years [3.1] since the advent of DRAMs in the early 1970s. As a result, 64–256 Mb DRAMs are now at the volume-production level. Such rapid progress in DRAM density has led to their playing an important role in enhancing the performance and reducing the cost of electronic systems such as large computers, workstations, personal computers (PCs), and so on. The quadrupling of memory capacity, as shown in Fig. 3.1, through high-density technology has contributed to this progress. High-performance circuits aimed at higher speed and lower dissipation, which have been achieved in past despite the ever-increasing chip area with increased memory capacity (Fig. 3.1), have also benefited system designers.
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References
K. Itoh et al., IEEE J. Solid-State Circuits 32(5), 624 (1997).
K. Itoh et al, “VLSI memory technology: current status and future trends”, ESSCIRC99 Dig. Tech. Papers, pp. 3–10, Sept. 1999.
K. Itoh et al., IEEE Proc. 83(4), 524 (1995).
K. Itoh, VLSI Memory Design (Baifukan, Tokyo 1994) (in Japanese).
C.N. Ahlquist et al., “A 16 K dynamic RAM”, ISSCC76 Dig.Tech.Papers, pp. 128–129, Feb. 1976.
S.S. Eaton et al., “A 100 ns 64 K dynamic RAM using redundancy techniques”, ISSCC81 Dig. Tech. Papers, pp. 84–85, Feb. 1981.
K. Kimura et al., IEEE J. Solid-State Circuits SC-21(3), 381 (1986).
R.C. Foss et al., “Application of a high-voltage pumped supply for low-power DRAM”, Symp. VLSI Circuits, Dig. Tech. Papers, pp. 106–107, 1992.
K. Itoh et al, “A single 5 V 64 K dynamic RAM”, ISSCC80 Dig. Tech.Papers, pp. 228–229, Feb. 1980.
T. Mano et al, “Circuit technologies for 16 Mb DRAMs”, ISSCC87 Dig. Tech. Papers, pp. 22–23, Feb. 1987.
K. Itoh et al., “An experimental 1 Mb DRAM with on-chip voltage limiter”, ISSCC84 Dig. Tech. Papers, pp. 282–283, Feb. 1984.
K. Arimoto et al., “A 60 ns 3.3 V 16 Mb DRAM”, ISSCC89 Dig.Tech. Papers, pp. 244–245, Feb. 1989.
S. Fujii et al., IEEE J. Solid-State Circuits 24(5), 1170 (1989).
P.R. Schroeder, R.J. Proebsting, “A 16 K × 1 Bit dynamic RAM”, ISSCC77 Dig. Tech. Papers, pp. 12–13, Feb. 1977.
R. Taylor, M. Johnson, “A 1 Mb CMOS DRAM with a divided bitline matrix architecture”, ISSCC85 Dig.Tech. Papers, pp. 242–243, Feb. 1985.
M. Inoue et al., “A 16 Mb DRAM with an open bit-line architecture”, ISSCC88 Dig. Tech. Papers, pp. 246–247, Feb. 1988.
T. Fujii et al., “A 90 ns 256 K × 1 b DRAM with double level al technology”, ISSCC83 Dig.Tech. Papers, pp. 226–227, Feb. 1983.
K. Noda et al., “A boosted dual word-line decoding scheme for 256 Mb DRAMs”, Symp. VLSI Circuits, Dig.Tech. Papers, pp. 112–113, June 1992.
T. Sugibayashi et al., “A 30 ns 256 Mb DRAM with multi-divided array structure”, ISSCC93 Dig.Tech. Papers, pp. 50–51, Feb. 1993.
D.J. Lee et al., “A 35 ns 64 Mb DRAM using on-chip boosted power supply”, Symp.VLSI Circuits, Dig.Tech. Papers, pp. 64–65, 1992.
T. Nakano, Y. Akasaka, ULSI DRAM Technology (Science Forum, Tokyo 1992) (in Japanese).
K.M. Hardee, R. Sud, IEEE J. Solid-State Circuits SC-16 (5), 435 (1981).
H. Ozaki et al., IEICE J71-C (8), 1156 (1988) (in Japanese).
K. Matsui et al, “A study on drive method of rowdecoder”, Proc. IEICE Spring Conf., C-623, 1992 (in Japanese).
Y. Kubota et al., “Reduction of wordline noises by decoded-pulldown circuits”, Proc. IEICE Spring Conf., C-626, 1992 (in Japanese).
Y. Oowaki et al., “A 33 ns 64 Mb DRAM”, ISSCC Dig. Tech. Papers, pp. 114–115, Feb. 1991.
D. Takashima et al, IEEE J. Solid-State Circuits 27(4), 603 (1992).
K. Sato et al., IEEE J. Solid-State Circuits 26(11), 1556 (1991).
S.M. Yoo et al., IEEE J. Solid-State Circuits 28(4), 499 (1993).
G. Kitsukawa et al., IEEE J. Solid-State Circuits 25(5), 1102 (1990).
K. Komatsuzaki et al., “Circuits techniques for a wide word I/O path 64 Meg DRAM”, Symp.VLSI Circuits, Dig. Tech. Papers, pp. 133–134, 1991.
P. Gillingham et al., IEEE J. Solid-State Circuits 26(8), 1171 (1991).
D. Galbi et al., “A 33 ns 64 Mb DRAM with master-wordline architecture”, ESSCIRC’92 Dig. Tech. Papers, pp. 131–134, 1992.
K. Kimura et al., IEEE J. Solid-State Circuits SC-22(5), 651 (1987).
G. Kitsukawa et al., IEEE J. Solid-State CircuitsSC-22 (5), 657 (1987).
T. Kawahara et al., IEEE J. Solid-State Circuits, 26(11), 1530 (1991).
A. Tanabe et al, IEEE J. Solid-State Circuits 27(11), 1525 (1992).
T. Ooishi et al., “A well-synchronized sensing/equalizing method for sub- 1.0 V operating advanced DRAMs”, Symp. VLSI Circuits, Dig.Tech. Papers, pp. 81–82, May 1993.
T. Yamada et al., “A 64 Mb DRAM with meshed power line and distributed sense-amplifier driver”, ISSCC91 Dig. Tech. Papers, pp. 108–109, Feb. 1991.
H. Hidaka et al., IEEE J. Solid-State Circuits 27(7), 1020 (1992).
H. Miyamoto et al., “A 32 ns 64 Mb DRAM with extended second metal line architecture”, ESSCIRC’93 Dig. Tech. Papers, pp. 41–44, Sept. 1993.
S. Watanabe et al., “BiCMOS circuit technology for high speed DRAMs”, Symp.VLSI Circuits, Dig. Tech.Papers, pp. 79–80, 1987.
T. Nagai et al., “A 17 ns 4 Mb CMOS DRAM using direct bit-line sensing technique”, ISSCC91 Dig. Tech. Papers, pp. 58–59, Feb. 1991.
G. Kitsukawa et al., IEICE J75-C-2 (1), 17 (1992).
Y. Nakagome et al., IEEE J. Solid-State Circuits 26(4), 465 (1991).
K. Kimura et al., IEICE Trans. J68-C(12), 1006 (1985) (in Japanese).
M. Taguchi et al., “A 40 ns 64 Mb DRAM with current-sensing data-bus amplifier”, ISSCC91 Dig. Tech. Papers, pp. 112–113, Feb. 1991.
Y. Tsukikawa et al., “Shared read gate architecture suitable for high speed DRAMs”, Proc. IEICE Spring Conf., C-631, 1992 (in Japanese).
Y. Takano et al., “A study of data transfer scheme for DRAM”, Proc. IEICE Spring Conf., C-634, 1993 (in Japanese).
K. Sato et al., “A 20 ns static column 1 Mb DRAM in CMOS technology”, ISSCC85 Dig. Tech. Papers, pp. 254–255, Feb. 1985.
H.L. Kalter et al., IEEE J. Solid-State Circuits 25, 1118 (1990).
M. Taniguchi et al., IEEE J. Solid-State Circuits SC-16, 492 (1981).
K. Nogami et al., IEEE J. Solid-State Circuits SC-21, 662 (1986).
K. Sawada et al., “Self-aligned refresh scheme for VLSI intelligent dynamic RAMs”, Symp. VLSI Technology Dig.Tech. Papers, pp. 85–86, May 1986.
Y. Miyamoto et al., “Study of new refresh method for low data retention current”, Proc. IEICE Spring Conf., C-638, 1993 (in Japanese).
K. Kenmizaki et al, “A 36 μA 4 Mb PSRAM with quadruple array operation”, Symp.VLSI Circuits, Dig. Tech. Papers, pp. 79–80, 1989.
Y. Konishi et al, IEEE J. Solid-State Circuits 25(5), 1112 (1990).
T. Kawahara et al., “A charge recycle refresh for Gb-scale DRAMs in file applications”, Symp.VLSI Circuits, Dig. Tech. Papers, pp. 41–42, May 1993.
Cenker et al., IEEE Trans. Electron Devices ED-26, 853 (1979).
Mano et al., IEEE J. Solid-State Circuits SC-17, 726 (1982).
T. Smith et al, IEEE J. Solid-State Circuits SC-16, 506 (1981).
K. Shimohigashi et al., “Redundancy techniques for dynamic RAMs”, Proc. 14th Conf. Solid State Devices, pp. 63–67, Aug. 1982.
M. Horiguchi, “Redundancy Techniques for High-Density DRAMs”, Proc. International Conf. on Innovative Systems in Silicon, pp. 23–29, 1997.
U.S. Patent 5 631 862, U.S. Patent 5 734 617.
M. Kumanoya et al., IEEE J. Solid-State Circuits SC-20, 909 (1985).
S. Fujii et al., IEEE J. Solid-State Circuits SC-18, 441 (1983).
M. Horiguchi et al., IEEE J. Solid-State Circuits 26(1), 12 (1991).
G. Kitsukawa et al., IEEE J. Solid-State Circuits 28, 1105 (1993).
K. Arimoto et al., IEEE J. Solid-State Circuits 25, 11 (1990).
R. Hori et al., IEEE J. Solid-State Circuits SC-19, 634 (1984).
K. Itoh, IEEE J. Solid-State Circuits 25, 778 (1990).
Sugibayashi et al., IEEE J. Solid-State Circuits 28, 1092 (1993).
K. Sasaki et al., IEEE J. Solid-State Circuits 24, 1219 (1989).
H. Yamauchi et al, IEEE J. Solid-State Circuits 28, 1084 (1993).
K. Ishibashi et al, IEEE J. Solid-State Circuits 29, 411 (1994).
M. Asakura et al., “A hierarchical bit-line architecture with flexible redundancy and block compare test for 256 Mb DRAM”, Symp. VLSI Circuits, Dig. Tech. Papers, pp. 93–94, May 1993.
T. Kirihata et al, IEEE J. Solid-State Circuits 31, 558 (1996).
K. Furutani et al., “A board level parallel test and short circuit failure repair circuit for high-density, low-power DRAMs”, Symp.VLSI Circuits, Dig. Tech. Papers, pp. 70–71, June 1996.
Asakura et al., “A 34 ns 256 Mb DRAM with boosted sense-ground scheme”, ISSCC, Dig. Tech. Papers, pp. 140–141, Feb. 1994.
R. Sud, K.C. Hardee, “Redundancy”, Electronics, July 28, 1981, pp. 121–126.
K. Kokkonen et al., “Redundancy techniques for fast static RAMs”, ISSCC81 Dig. Tech. Papers, pp. 88–81, Feb. 1980.
B. Keeth, “Redundancy approaches for maximum yield”, Memory Design and Evolution, Symp. VLSI Circuits, June 1998.
Y. Inoue et al, “An 85 ns 1 Mb DRAM in a plastic DIP”, ISSCC’85 Dig. Tech. Papers, pp. 238–239, Feb. 1985.
M. Horiguchi et al., IEEE J. Solid-State Circuits 26(1), 12 (1991).
K. Arimoto et al., IEEE J. Solid-State Circuits 25, 11 (1990).
J. Inoue et al., “Parallel testing technology for VLSI memories”, Proc. Int. Test Conf., pp. 1066–1071, 1987.
K. Arimoto et al., ISSC91 J. Solid-State Circuits 24, 1184 (1989).
S. Mori et al., “A 45 ns 64 Mbit DRAM with a Merged Match-Line Test Architecture”, ISSCC91 Dig. Tech. Papers, pp. 110–111, Feb. 1991.
T. Sugibayashi et al., “A distibrutive serial multi-bit parallel test scheme for large capacity DRAMs”, Symp. VLSI Circuits, Dig. Tech. Papers, pp. 63–64, 1993.
Y. Nakagome, K. Itoh, IEICE Trans., E74(4), 799 (1991).
T. Takashima et al., IEEE J. Solid-State Circuits 25, 903 (1990).
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Itoh, K. (2001). DRAM Circuits. In: VLSI Memory Chip Design. Springer Series in Advanced Microelectronics, vol 5. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-04478-0_3
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DOI: https://doi.org/10.1007/978-3-662-04478-0_3
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