Simulation of CVD Step Coverage for SiH4 using Parallel Processing of DSMC Method

  • S. Tatsuta
  • Y. Sato
  • N. Tamaoki
Conference paper

Abstract

This paper describes the basic study of the simulation of chemical vapor deposition (CVD) step coverage that is used to estimate the deposition of thin films in LSI production. Given the trend toward extremely high density in the semiconductor manufacturing process, such as that of LSIs, the deposition process of silicon thin film on the circuit pattern needs to be accurate. To optimize the deposition of thin film around the trench of the order of less than a micron, computer simulations of the step coverage and of the film growth rate in the process are very important. In this simulation reported in this paper, the thin film deposition process, whose reaction is modeled as silicon from silane (SiH4) and silylene (SiH2), is solved using the direct simulation Monte Carlo (DSMC) method. The DSMC method is usually adopted in this case, but, since 1) this method solves the Boltzmann equation with a huge amount of molecular collisions and free motions and 2) sticking probability of molecules is of the order of 10-5 [1], even a high performance computer needs much time for this calculation. Although the performance of supercomputers and other types of computers is improving, the DSMC method as conventionally applied seems to be reaching its limit in terms of practicality.

Keywords

Silane Trench Silylene 

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References

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Copyright information

© Springer-Verlag Berlin Heidelberg 1995

Authors and Affiliations

  • S. Tatsuta
    • 1
  • Y. Sato
    • 1
  • N. Tamaoki
    • 1
  1. 1.Toshiba Corp.KanagawaJapan

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