Synthesis of Gate Model

  • Ulrich Golze


In this chapter, we come pretty close to the actual hardware on the chip. For this purpose, the Coarse Structure Model developed before in the hardware description language VERILOG is transformed to a Gate Model or synthesized. The given library of the silicon producer consisting of logic gates, flip-flops, drivers, adders, etc. serves as a base. We will develop a hierarchic model with the higher modules corresponding exactly to the modules of the Coarse Structure Model. Synthesis of this model is partially done manually, partially automatically. The Gate Model is so extensive that in the present volume the reader is introduced to the design method only by examples, and the wealth of technical details is hidden in the expert volume (Chapter H5).


Read Data Full Adder Combinational Logic Input Buffer Logic Synthesis 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • Ulrich Golze
    • 1
  1. 1.Department of Integrated Circuit Design (E.I.S.)Technical University of BraunschweigBraunschweigGermany

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