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Internal Specification of Coarse Structure

  • Ulrich Golze
Chapter
  • 196 Downloads

Abstract

In the previous chapter, the RISC processor TOOBSIE was specified externally by defining its “outside” behavior, basically its instruction syntax and semantics, as seen by an application programmer. For reference purposes, the Interpreter Model was developed as a golden device in the HDL VERILOG.

Keywords

Memory Access Register File Pipeline Stage Internal Specification Coarse Structure 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • Ulrich Golze
    • 1
  1. 1.Department of Integrated Circuit Design (E.I.S.)Technical University of BraunschweigBraunschweigGermany

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