Abstract
In the previous chapter, the RISC processor TOOBSIE was specified externally by defining its “outside” behavior, basically its instruction syntax and semantics, as seen by an application programmer. For reference purposes, the Interpreter Model was developed as a golden device in the HDL VERILOG.
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© 1996 Springer-Verlag Berlin Heidelberg
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Golze, U. (1996). Internal Specification of Coarse Structure. In: VLSI Chip Design with the Hardware Description Language VERILOG. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-61001-1_6
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DOI: https://doi.org/10.1007/978-3-642-61001-1_6
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-64650-8
Online ISBN: 978-3-642-61001-1
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