HDL Modeling with VERILOG
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This chapter introduces in detail the hardware description language VERILOG. The reader is enabled to create his or her own hardware models and to fully understand the Interpreter Model and the Coarse Structure Model of the RISC processor TOOBSIE. The introduction is conceived as both a course and a reference. A training simulator VeriWell together with the examples of this chapter are included on the disk, so that all programs may be tested on a PC or a SUN. The disk contains instructions for the use of VeriWell.
KeywordsTime Control Event Control Level Module Pipeline Stage Initial Block
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