Materials Issues and Characterization of Low-k Dielectric Materials

Abstract

Continuing improvement of microprocessor performance historically involves a decrease in the transistor size (device scaling). Device scaling allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However, an increase in packing density requires an even larger increase in the number of interconnects that connect the devices together in an integrated circuit (IC). The interconnect packing density requirement has led to a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. Unfortunately, as the interconnect wiring density increases so do the capacitance and the resistance. The larger capacitance causes the interconnect RC delay (or signal propagation delay), crosstalk, and power dissipation to all increase [1–5]. Models show that at device dimensions less than 0.25 µm (transistor gate length), the interconnect RC delay will begin to limit the overall chip performance. Thus, although the speed of the device increases as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits the improvement in device performance [1,2,5,6].