Abstract
It is now forecast that Terabit Ethernet will be needed in 2015. (A 1 Tb/s data rate means that the estimated memory capacity of a typical human could be transmitted in 24 seconds.) In this talk, Gordon Brebner will give an overview of research which demonstrates that Field Programmable Logic Array (FPGA) devices can be main processing components for 100-200 Gb/s networking, a main event horizon in 2010, and points the way to how techniques might scale (or not) towards a 1 Tb/s transmission rate by 2015. The highly configurable, and reconfigurable, characteristics of such devices make them a unique technology that fits with the requirements for extremely high performance and moreover for flexibility and programmability. Aside from discussing the physical technological properties, the talk will cover work on higher-level programming models that can make the technology more accessible to networking experts, as opposed to hardware/FPGA experts.
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© 2011 Springer-Verlag Berlin Heidelberg
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Brebner, G. (2011). Reconfigurable Computing for High Performance Networking Applications. In: Koch, A., Krishnamurthy, R., McAllister, J., Woods, R., El-Ghazawi, T. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2011. Lecture Notes in Computer Science, vol 6578. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19475-7_1
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DOI: https://doi.org/10.1007/978-3-642-19475-7_1
Publisher Name: Springer, Berlin, Heidelberg
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