Abstract
The chapter is dedicated to the functional analysis and synthesis of the floating point arithmetic devices and it begins by highlighting the characteristics of operating in floating point, with investigation of the fundamental operations of addition, subtraction, multiplication and division. Particular consideration is given to the rounding problem with respect to analyzing the rounding modes, establishing the values of the rounding bits following the normalization shifts and of the conditioned implementation of the rounding operation. Synthesis solutions for some floating point units are presented, for which the addition and subtraction operations are to be realized without and with rounding. The steps of the algorithm for floating point addition and subtraction with rounding are dissected and the methods for speeding up the addition/subtraction process are investigated. Besides the speedup techniques based on an arithmetic pipeline, there is an extensive presentation of the solutions based on parallel computation. In this last context we present some innovative solutions based on reconfigurable synthesis. The chapter concludes with a section dedicated to analysis of the floating point multiplication and division operations.
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Vlăduţiu, M. (2012). Functional Analysis and Synthesis of Floating Point Arithmetic Devices. In: Computer Arithmetic. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-18315-7_5
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DOI: https://doi.org/10.1007/978-3-642-18315-7_5
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