Abstract
The chapter starts with the presentation of the fundamental methods for binary multiplication. Subsequently we introduce, in a unitary manner, syntheses of sequential multiplication devices for numbers represented in sign-magnitude code, respectively on twos complement code based on the Robertson and Booth procedures. The algorithms are presented in terms of a hardware description language accompanied by configuration diagrams, as well as by examples of operation, all emphasizing differences with respect to the performance-price-reliability triplet. Afterwards, techniques for multiplication process speedup are analyzed, based on raising the value of the number systems radix and use of a carry-save adder. There is a distinctive emphasis on combinational array and tree structures for binary multiplication implementation. Following the same direction of increased importance for the reliability and dependability aspects, similarly to the addition/subtraction chapter, we inserted a section addressing control by means of residue codes of the binary multiplication operation.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Nicolas Boullis, Arnaud Tisserand: “Some Optimizations of Hardware Multiplication by Constant Matrices” IEEE Trans. Comput., vol. 54, no. 10, 2005, pp. 1271–1282.
Albert Danysh, Dimitri Tan: “Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit” IEEE Trans. Comput., vol. 54, no. 3, 2005, pp. 284–293.
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos: “Modulo 2n±1 Adder Design Using Select-Prefix Blocks” IEEE Trans. Comput., vol. 52, no. 11, 2003, pp. 1399–1406.
Miloš D. Ercegovac, Tomas Lang: “Digital Arithmetic” Morgan Kaufmann, San Mateo, 2004.
Mustafa Gok, Michael J. Schulte, Mark G. Arnold: “Integer Multipliers with Overflow Detection” IEEE Trans. Comput., vol. 55, no. 8, 2006, pp. 1062–1066.
John P. Hayes: “Computer Architecture and Organization” McGraw-Hill, New York, Second Edition, 1988.
John P. Hayes: “Computer Architecture and Organization” McGraw-Hill, New York, Third Edition, 1998.
John L. Hennessy, David A. Patterson: “Computer Organization and Design. The Hardware/Software Interface” Morgan Kaufmann, San Mateo, 1994.
John L. Hennessy, David A. Patterson: “Computer Architecture. A Quantitative Approach” Morgan Kaufmann, San Mateo, Third Edition, 2003; Appendix H: Computer Arithmetic by David Goldberg.
Zhijun Huang, Miloš D. Ercegovac: “High-Performance Low-Power Left-to-Right Array Multiplier Design” IEEE Trans. Comput., vol. 54, no. 3, 2005, pp. 272–283.
International Technology Roadmap for Semiconductors-Interconnect, 2001.
Jung-Yup Kang, Jean-Luc Gaudiot: “A Simple High-Speed Multipier Design” IEEE Trans. Comput., vol. 55, no. 10, 2006, pp. 1253–1258.
Marcelo E. Kaihara, Naofumi Takagi: “A Hardware Algorithm for Modular Multiplication/Division” IEEE Trans. Comput., vol. 54, no. 1, 2005, pp. 12–21.
Ulrich W. Kulisch: “Advanced Arithmetic for the Digital Computer. Design of Arithmetic Units” Springer, Berlin, 2002.
Mauro Olivieri: “Design of Synchronous and Asynchronous Variable-Latency Pipelined Multipliers” EEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 2, 2001, pp. 365–376.
Amos R. Omondi: “Computer Arithmetic Systems. Algorithms, Architecture and Implementations” 1994. C.A.R. Hoare Series Editor.
David A. Patterson, John L. Hennessy: “Computer Architecture. A Quantitative Approach” Morgan Kaufmann, Dordrecht, Second Edition, 1996; Appendix A: Computer Arithmetic by David Goldberg.
Behrooz Parhami: “Computer Arithmetic. Algorithms and Hardware Designs” Oxford University Press, London, 2000.
L. Howard Pollard: “Computer Design and Architecture” Prentice-Hall International, Englewood Cliffs, 1990.
T.R.N. Rao, E. Fujiwara: “Error-Control Coding for Computer Systems” Prentice-Hall International, Englewood Cliffs, 1989.
Jan M. Rabaey, Massored Pedram: “Low Power Design Methodologies” Kluwer Academic, Dordrecht, 1996.
Peter-Michael Seidel, Lee D. McFearin, David W. Matula: “Secondary Radix Recordings for Higher Radix Multipliers” IEEE Trans. Comput., vol. 54, no. 2, 2005, pp. 111–123.
William Stallings: “Computer Organization and Architecture. Designing for Performance” Prentice Hall International, Englewood Cliffs, 1999.
N. Takagi, N.H. Yasuura, S. Yajima: “High-Speed VSLI Multiplication Algorithm with a Redundant Binary Addition Tree” IEEE Trans. Comput., vol. 34, no. 9, 1985, pp. 789–796.
Mircea Vlăduţiu: “Tehnologie de ramură şi fiabilitate” Litografia Institutului Politehnic, Timişoara, 1982.
Mircea Vlăduţiu: “Tehnica testării sistemelor de calcul” Litografia Institutului Politehnic, Timişoara, 1986.
John F. Wakerly: “Digital Design. Principles and Practices” Prentice-Hall, New York, 2000.
John M. Yarbrough: “Digital Logic. Application and Design” West Publishing Company, Eagan, 1997.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer-Verlag Berlin Heidelberg
About this chapter
Cite this chapter
Vlăduţiu, M. (2012). Functional Analysis and Synthesis of Binary Multiplication Devices. In: Computer Arithmetic. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-18315-7_3
Download citation
DOI: https://doi.org/10.1007/978-3-642-18315-7_3
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-18314-0
Online ISBN: 978-3-642-18315-7
eBook Packages: Computer ScienceComputer Science (R0)