Abstract
Network-on-Chip (NoC) has emerged as a very promising paradigm for designing scalable communication architecture for Systems-on-Chips (SoCs). However, NoCs designed to fulfill the bandwidth requirements between the cores of an SoC for a certain set of running applications may be highly sub-optimal for another set of applications. In this context, methods that can lead to versatility enhancements of initial NoC designs to changing working conditions, imposed by variable sets of executed real-life applications at each moment in time, are very important for designing competitive NoCs in industrial SoCs.
In this work, we present a run-time reconfigurable NoC framework based on the partial dynamic reconfiguration capabilities of Field-Programmable Gate Arrays (FPGAs). This new NoC framework can dynamically create/delete express lines between SoC components (implementing dynamically circuit-switching channels) and perform run-time NoC topology and routing-table reconfigurations to handle interconnection congestion, with a very limited performance overhead. Moreover, we show in our experimental results that the addition of these dynamic reconfiguration capabilities into basic NoCs using our framework only implies a very limited area overhead (around 10% on average) with respect to the initial NoC designs; thus, it can bring great benefits when compared to traditional non-reconfigurable NoC design approaches for worst-case bandwidth requirements in SoCs with many possible sets of running applications.
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Ahmad, B., Erdogan, A.T., Khawam, S.: Architecture of a dynamically reconfigurable noc for adaptive reconfigurable mpsoc. In: First NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2006, June 15-18, pp. 405–411 (2006)
Angiolini, F., Meloni, P., Carta, S., Benini, L., Raffo, L.: Contrasting a NoC and a traditional interconnect fabric with layout awareness. In: Proceedings of Design, Automation and Test in Europe Conference (DATE 2006), Munich, Germany, pp. 124–129 (2006)
Benini, L., De Micheli, G. (eds.): Networks on chips: Technology and Tools. Morgan Kaufmann Publishers, San Francisco (2006)
Bertozzi, D., Jalabert, A., Murali, S., Tamhankar, R., Stergiou, S., Benini, L., De Micheli, G.: Noc synthesis flow for customized domain specific multiprocessor systems-on-chip. IEEE Trans. Parallel Distrib. Syst. 16(2), 113–129 (2005)
Brebner, G., Levi, D.: Networking on chip with platform fpgas. In: Proceedings of the 2003 International Conference on Field-Programmable Technology (FPT), December 2003, pp. 13–20 (2003)
Ching, D., Schaumont, P., Verbauwhede, I.: Integrated modeling and generation of a reconfigurable network-on-chip. In: Proceedings of 18th International Conference on Parallel and Distributed Processing Symposium, April 26-30, p. 139 (2004)
Hansson, A., Goossens, K.: Trade-offs in the configuration of a network on chip for multiple use-cases. In: First International Symposium on Networks-on-Chip, NOCS 2007, May 7-9, pp. 233–242 (2007)
Xilinx Inc. Early Access Partial Reconfiguration Guide. Xilinx Inc. (2006)
Jovanovic, S., Tanougast, C., Weber, S., Bobda, C.: Cunoc: A scalable dynamic noc for dynamically reconfigurable fpgas. In: International Conference on Field Programmable Logic and Applications, FPL 2007, August 27-29, pp. 753–756 (2007)
Kumar, A., Hansson, A., Huisken, J., Corporaal, H.: An fpga design flow for reconfigurable network-based multi-processor systems on chip. In: Design, Automation and Test in Europe Conference and Exhibition, DATE 2007, April 16-20, pp. 1–6 (2007)
Lysne, O., Pinkston, T.M., Duato, J.: A methodology for developing dynamic network reconfiguration processes. In: ICPP, p. 77 (2003)
Montone, A., Rana, V., Santambrogio, M.D., Sciuto, D.: Harpe: a harvard-based processing element tailored for partial dynamic reconfigurable architectures. In: 22nd IEEE International Parallel and Distributed Processing Symposium - 15th Reconfigurable Architectures Workshop (April 2008)
Murali, S., Coenen, M., Radulescu, A., Goossens, K., De Micheli, G.: Mapping and configuration methods for multi-use-case networks on chips. In: Proceedings of the 2006 conference on Asia South Pacific design automation (ASP-DAC), pp. 146–151. ACM Press, New York (2006)
Pionteck, T., Koch, R., Albrecht, C.: Applying partial reconfiguration to networks-on-chips. In: International Conference on Field Programmable Logic and Applications, FPL 2006, August 28-30, pp. 1–6 (2006)
Vicentelli, A., Martin, G.: A vision for embedded systems: Platform-based design and software. IEEE Design and Test - Special Issue of Computers 18(6), 23–33 (2001)
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Rana, V., Atienza, D., Santambrogio, M.D., Sciuto, D., De Micheli, G. (2010). A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication. In: Piguet, C., Reis, R., Soudris, D. (eds) VLSI-SoC: Design Methodologies for SoC and SiP. VLSI-SoC 2008. IFIP Advances in Information and Communication Technology, vol 313. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12267-5_13
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DOI: https://doi.org/10.1007/978-3-642-12267-5_13
Publisher Name: Springer, Berlin, Heidelberg
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