Abstract
Evaluation and refinement of system models often require modifications in the model that follow concrete rules. In this work, a method for a flexible automation of such transformation steps will be presented. It allows savings in development time and reduces the error proneness. Therefore, a tool for rule based manipulation of VHDL design descriptions has been extended to enable its use with system models in C++ and SystemC. An automotive electronics application, the integration of SystemC modules into a MATLAB/Simulink simulation by automatic wrapper generation, will show its use in the design process.
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© 2009 IFIP International Federation for Information Processing
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Görgen, R., Oetjens, JH., Freuer, J., Nebel, W. (2009). Automatic Transformation of System Models in Automotive Electronics. In: Rettberg, A., Zanella, M.C., Amann, M., Keckeisen, M., Rammig, F.J. (eds) Analysis, Architectures and Modelling of Embedded Systems. IESS 2009. IFIP Advances in Information and Communication Technology, vol 310. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04284-3_21
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DOI: https://doi.org/10.1007/978-3-642-04284-3_21
Publisher Name: Springer, Berlin, Heidelberg
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