Process Characterisation for Low VTH and Low Power Design

  • E. Seebacher
  • G. Rappitsch
  • H. Höller
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)


We discuss state of the art and new developments for the path to first time right silicon for low VTH and low power analog design. This article touches on a few of the issues that are essential when starting a low VTH or low power design, where the bottom line is a well controlled process technology and the existence of a comprehensive Process Design Kit with accurate SPICE models which include device mismatch parameters and noise parameters. The necessary process characterisation and the requirements for SPICE modelling are described. In this article state of the art MOS transistor modelling especially in the transition region, noise modelling and device mismatch are discussed with regard to low VTH and low power design.


Threshold Voltage NMOS Transistor PMOS Transistor Mismatch Parameter Weak Inversion 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    ELDO User’s Manual 5.6, Release 2001.2, pp. 10/258–10/262 (August 2001)Google Scholar
  2. 2.
    Cheng, Y., Jeng, M.C., Liu, Z., Huang, J., Chen, M., Ko, P.K., Hu, C.: A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation. IEEE Electron Devices 44(2), 277–287 (1997)CrossRefGoogle Scholar
  3. 3.
    Department of Electrical Engeneering and Computer Sience: BSIM3v3 Manual. University of California, BerkeleyGoogle Scholar
  4. 4.
    Enz, C., Krummenacher, F., Vittoz, E.: An analytical MOS transistor model valid in all regions of Operation and dedicated to low-voltage and low current applications. Journal on Analog Integration Circuits and Signal Processing. Kluwer Academic Pub., 83–114 (1995)Google Scholar
  5. 5.
    Enz, C., Vittoz, E.: MOS transistor modeling for low-voltage and low power analog IC design. Microelectronic Engeneering 39, 59–76 (1997)CrossRefGoogle Scholar
  6. 6.
    Velghe, R.M.D.A., Klaassen, D.B.M., Klaassen, F.M.: MOS model 9, NL-UR 003/94 (1994), Internet
  7. 7.
    Liu, W., Jin, X., Cao, K.M., Hu, C.: Project Director:Professor Chenming Hu: BSIM4.0 MOSFET Model, User’s Manual. University of California, BerkeleyGoogle Scholar
  8. 8.
    Ankele, B., Hölzl, W., O’Leary, P.: Enhanced MOS Parameter Extraction and SPICE Modelling for Mixed Analogue and Digital Circuit Simulation. In: 1998 IEEE International Conference on Microelectronic Test Structures, Edinburgh (1989)Google Scholar
  9. 9.
    Bastos, J., Steyaert, M., Pergoot, A., Sansen, W.: Mismatch Characterisation of Sub micron MOS Transistors. In: Analog Integrated Circuits and Signal Processing, vol. 12, pp. 95–106. Kluwer Academic Publisher, Boston (1997)Google Scholar
  10. 10.
    Pelgrom, M., Duinmaijer, A., Welbers, A.: Matching_Properties_of_MOS_Transistors. IEEE Journal of Solid-State Circuits 24 (October 1989)Google Scholar
  11. 11.
    Hung, K.K., Ko, P.K., Hu, C., Cheng, Y.C.: A physics based MOSFET Noise Model for Circuit Simulators. IEEE Transactions on Electron Devices 37(5) (May 1990)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • E. Seebacher
    • 1
  • G. Rappitsch
    • 1
  • H. Höller
    • 1
  1. 1.Austriamicrosystems AGAustria

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