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Process Characterisation for Low VTH and Low Power Design

  • E. Seebacher
  • G. Rappitsch
  • H. Höller
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)

Abstract

We discuss state of the art and new developments for the path to first time right silicon for low VTH and low power analog design. This article touches on a few of the issues that are essential when starting a low VTH or low power design, where the bottom line is a well controlled process technology and the existence of a comprehensive Process Design Kit with accurate SPICE models which include device mismatch parameters and noise parameters. The necessary process characterisation and the requirements for SPICE modelling are described. In this article state of the art MOS transistor modelling especially in the transition region, noise modelling and device mismatch are discussed with regard to low VTH and low power design.

Keywords

Threshold Voltage NMOS Transistor PMOS Transistor Mismatch Parameter Weak Inversion 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • E. Seebacher
    • 1
  • G. Rappitsch
    • 1
  • H. Höller
    • 1
  1. 1.Austriamicrosystems AGAustria

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