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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

13th International Workshop, PATMOS 2003, Turin, Italy, September 10-12, 2003. Proceedings

  • Jorge Juan Chico
  • Enrico Macii
Conference proceedings PATMOS 2003

Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)

Table of contents

  1. Front Matter
  2. Keynote Speech

  3. Gate-Level Modeling and Design

    1. G. Privitera, Francesco Pessolano
      Pages 2-10
    2. Pradeep Varma, Ashutosh Chakraborty
      Pages 11-20
    3. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
      Pages 21-30
    4. Luis Mengibar, Luis Entrena, Michael G Lorenz, Raúl Sánchez-Reillo
      Pages 31-40
  4. Low Level Modeling and Characterization

    1. Tim Schoenauer, Joerg Berthold, Christoph Heer
      Pages 41-50
    2. A. Verle, X. Michel, P. Maurine, N. Azémard, D. Auvergne
      Pages 60-69
    3. E. Seebacher, G. Rappitsch, H. Höller
      Pages 70-79
    4. Josep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodriguez
      Pages 80-89
  5. Interconnect Modeling and Optimization

    1. M. R. Casu, M. Graziano, G. Piccinini, G. Masera, M. Zamboni
      Pages 90-100
    2. Jérôme Lescot, François J. R. Clément
      Pages 101-110
    3. Sampo Tuuna, Jouni Isoaho
      Pages 111-120
    4. M. Addino, M. R. Casu, G. Masera, G. Piccinini, M. Zamboni
      Pages 121-130
    5. A. Stammermann, D. Helms, M. Schulte, A. Schulz, W. Nebel
      Pages 131-140
  6. Asynchronous Techniques

    1. Joep Kessels, Ad Peeters, Suk-Jin Kim
      Pages 141-150
    2. Sonia López, Óscar Garnica, Ignacio Hidalgo, Juan Lanchares, Román Hermida
      Pages 151-160
    3. Miloš Krstić, Eckhard Grass
      Pages 161-170
    4. João Leonardo Fragoso, Gilles Sicard, Marc Renaudin
      Pages 171-180
    5. P. Maurine, J. B. Rigaud, F. Bouesse, G. Sicard, M. Renaudin
      Pages 181-191
  7. Keynote Speech

  8. Industrial Session

  9. RTL Power Modeling and Memory Optimisation

    1. B. Arts, A. Bellu, L. Benini, N. van der Eng, M. Heijligers, E. Macii et al.
      Pages 197-207
    2. Maurizio Bruno, Alberto Macii, Massimo Poncino
      Pages 208-218
    3. Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose
      Pages 219-228
    4. S. Cserveny, J. -M. Masgonty, C. Piguet
      Pages 229-238
    5. José L. Ayala, Marisa López-Vallejo
      Pages 239-248
  10. High-Level Modeling

    1. Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria
      Pages 249-258
    2. Fei Li, Lei He, Joe Basile, Rakesh J. Patel, Hema Ramamurthy
      Pages 259-268
    3. Alberto García-Ortiz, Lukusa Kabulepa, Manfred Glesner
      Pages 269-278
    4. S. Nikolaidis, N. Kavvadias, T. Laopoulos, L. Bisdounis, S. Blionas
      Pages 279-288
    5. Marc Leeman, David Atienza, Francky Catthoor, V. De Florio, G. Deconinck, J. M. Mendias et al.
      Pages 289-298
  11. Power Efficient Technologies and Designs

    1. Vineela Manne, Akhilesh Tyagi
      Pages 299-308
    2. Jürgen Fischer, Ettore Amirante, Francesco Randazzo, Giuseppe Iannaccone, Doris Schmitt-Landsiedel
      Pages 309-318
    3. Tae-Chan Kim, Meejoung Kim, Chulwoo Kim, Bong-Young Chung, Soo-Won Kim
      Pages 319-327
    4. V. Ferentinos, M. Milia, G. Lafruit, J. Bormans, F. Catthoor
      Pages 328-337
    5. Emil Hjalmarson, Robert Hägglund, Lars Wanhammar
      Pages 338-347
  12. Keynote Speech

  13. Communication Modeling and Design

    1. Andrea Acquaviva, Tajana Simunic, Vinay Deolalikar, Sumit Roy
      Pages 369-378
    2. S. R. Abdollahi, B. Bakkaloglu, S. K. Hosseini
      Pages 389-398
  14. Low Power Issues in Processors and Multimedia

    1. Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija
      Pages 399-408
    2. Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal et al.
      Pages 409-419
    3. K. Tatas, K. Siozios, D. Soudris, K. Masselos, K. Potamianos, S. Blionas et al.
      Pages 430-439

About these proceedings

Introduction

Welcome to the proceedings of PATMOS 2003. This was the 13th in a series of international workshops held in several locations in Europe. Over the years, PATMOS has gained recognition as one of the major European events devoted to power and timing aspects of integrated circuit and system design. Despite its signi?cant growth and development, PATMOS can still be considered as a very informal forum, featuring high-level scienti?c presentations together with open discussions and panel sessions in a free and relaxed environment. This year, PATMOS took place in Turin, Italy, organized by the Politecnico di Torino, with technical co-sponsorship from the IEEE Circuits and Systems Society and the generous support of the European Commission, as well as that of several industrial sponsors, including BullDAST, Cadence, Mentor Graphics, STMicroelectronics, and Synopsys. The objective of the PATMOS workshop is to provide a forum to discuss and investigate the emerging problems in methodologies and tools for the design of new generations of integrated circuits and systems. A major emphasis of the technical program is on speed and low-power aspects, with particular regard to modeling, characterization, design, and architectures.

Keywords

CAD design methods CAD tools CMOS Circuit design Flüssigkristallbildschirm IC technology Multimedia Performance Scheduling architecture computer architecture low power design low voltage memory performance analysis processor

Editors and affiliations

  • Jorge Juan Chico
    • 1
  • Enrico Macii
    • 2
  1. 1.Departamento de Tecnología ElectrónicaUniversidad de Sevilla Sevilla(Spain)
  2. 2.Politecnico di TorinoTorinoItaly

Bibliographic information

  • DOI https://doi.org/10.1007/b12033
  • Copyright Information Springer-Verlag Berlin Heidelberg 2003
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Springer Book Archive
  • Print ISBN 978-3-540-20074-1
  • Online ISBN 978-3-540-39762-5
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • Buy this book on publisher's site
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