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CMOS Gate Sizing under Delay Constraint

  • A. Verle
  • X. Michel
  • P. Maurine
  • N. Azémard
  • D. Auvergne
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)

Abstract

In this paper we address the problem of delay constraint distribution on a CMOS combinatorial path. We first define a way to determine on any path the reasonable bounds of delay characterizing the structure. Then we define two constraint distribution methods that we compare to the equal delay distribution and to an industrial tool based on the Newton-Raphson like algorithm. Validation is obtained on a 0.25μm process by comparing the different constraint distribution techniques on various benchmarks.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • A. Verle
    • 1
  • X. Michel
    • 1
  • P. Maurine
    • 1
  • N. Azémard
    • 1
  • D. Auvergne
    • 1
  1. 1.LIRMMUMR CNRS/Université de Montpellier IIMontpellierFrance

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