Abstract
In this paper we address the problem of delay constraint distribution on a CMOS combinatorial path. We first define a way to determine on any path the reasonable bounds of delay characterizing the structure. Then we define two constraint distribution methods that we compare to the equal delay distribution and to an industrial tool based on the Newton-Raphson like algorithm. Validation is obtained on a 0.25μm process by comparing the different constraint distribution techniques on various benchmarks.
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© 2003 Springer-Verlag Berlin Heidelberg
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Verle, A., Michel, X., Maurine, P., Azémard, N., Auvergne, D. (2003). CMOS Gate Sizing under Delay Constraint. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_8
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DOI: https://doi.org/10.1007/978-3-540-39762-5_8
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20074-1
Online ISBN: 978-3-540-39762-5
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