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Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders

  • Frank Gilbert
  • Norbert Wehn
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)

Abstract

The outstanding forward error correction provided by Turbo-Codes made them part of today’s communications standards. Therefore, efficient Turbo-Decoder architectures are important building blocks in communications systems. In this paper we present a scalable, highly parallel architecture for UMTS compliant Turbo decoding and apply architecture-driven voltage scaling to reduce the energy consumption. We will show that this approach adds some additional, more energy-efficient solutions to the design space of Turbo decoding systems. It can save up to 34 % of the decoding energy per datablock, although the supply voltage can not arbitrarily selected. We present throughput, area, and estimated energy results for various degrees of parallelization based on synthesis on a 0.18 μm ASIC-technology library, which is characterized for two different supply voltages: nominal 1.8 V and nominal 1.3 V.

Keywords

Supply Voltage Signal Processing System Turbo Decode Versus Supply Voltage Important Building Block 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Benini, L., De Micheli, G.: Networks on Chips: A New SoC Paradigm. IEEE Computer 35(1), 70–78 (2002)Google Scholar
  2. 2.
    Berrou, C., Glavieux, A., Thitimajshima, P.: Near Shannon Limit Error-Correcting Coding and Decoding: Turbo-Codes. In: Proc. 1993 International Conference on Communications (ICC 1993), Geneva, Switzerland, May 1993, pp. 1064–1070 (1993)Google Scholar
  3. 3.
    Davis, W.R., Zhang, N., Camera, K., Markovic, D., Smilkstein, T., Ammer, M.J., Yeo, E., Augsburger, S., Nikolic, B., Brodersen, R.W.: A Design Environment for High-Throughput Low-Power Dedicated Signal Processing Systems. IEEE Journal of Solid-State Circuits 37(3), 420–431 (2002)CrossRefGoogle Scholar
  4. 4.
    Dawid, H.: Algorithmen und Schaltungsarchitekturen zur Maximum a Posteriori Faltungsdecodierung. PhD thesis, RWTHAachen, Shaker Verlag, Aachen, Germany (1996) (in German)Google Scholar
  5. 5.
    Dawid, H., Gehnen, G., Meyr, H.: MAP Channel Decoding: Algorithm and VLSI Architecture. In: VLSI Signal Processing VI, pp. 141–149. IEEE, Los Alamitos (1993)CrossRefGoogle Scholar
  6. 6.
    Garrett, D., Xu, B., Nicol, C.: Energy efficient Turbo Decoding for 3G Mobile. In: Proc. 2001 International Symposium on Low Power Electronics and Design (ISLPED 2001), Huntington Beach, California, USA, August 2001, pp. 328–333 (2001)Google Scholar
  7. 7.
    Gilbert, F., Worm, A., Wehn, N.: Low Power Implementation of a Turbo-Decoder on Programmable Architectures. In: Proc. 2001 Asia South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan, January 2001, pp. 400–403 (2001)Google Scholar
  8. 8.
    Kienle, F., Michel, H., Gilbert, F., Wehn, N.: Efficient MAP-Algorithm Implementation on Programmable Architectures. In: Kleinheubacher Berichte 2003, Miltenberg, Germany, October 2002, vol. 46 (2002) (to appear)Google Scholar
  9. 9.
    Robertson, P., Hoeher, P., Villebrun, E.: Optimal and Sub-Optimal Maximum a Posteriori Algorithms Suitable for Turbo Decoding. European Transactions on Telecommunications (ETT) 8(2), 119–125 (1997)CrossRefGoogle Scholar
  10. 10.
    Schurgers, C., Engels, M., Catthoor, F.: Energy Efficient Data Transfer and Storage Organization for a MAP Turbo Decoder Module. In: Proc. 1999 International Symposium on Low Power Electronics and Design (ISLPED 1999), San Diego, California, USA, August 1999, pp. 76–81 (1999)Google Scholar
  11. 11.
    Subramanian, R.: Shannon vs. Moore: Driving the Evolution of Signal Processing Platforms in Wireless Communications (Invited Talk). In: Proc. 2002 Workshop on Signal Processing Systems (SiPS 2002), San Diego, California, USA (October 2002)Google Scholar
  12. 12.
    Sylvester, D., Keutzer, K.: Rethinking Deep-Submicron Circuit Design. IEEE Computer 32(11), 25–33 (1999)Google Scholar
  13. 13.
    Third Generation Partnership Project. 3GPP home page, http://www.3gpp.org
  14. 14.
    Thul, M.J., Gilbert, F., Vogt, T., Kreiselmaier, G., Wehn, N.: A Scalable System Architecture for High-Throughput Turbo-Decoders. In: Proc. 2002 Workshop on Signal Processing Systems (SiPS 2002), San Diego, California, USA, October 2002, pp. 152–158 (2002)Google Scholar
  15. 15.
    Thul, M.J., Gilbert, F., Wehn, N.: Optimized Concurrent Interleaving for High-Throughput Turbo-Decoding. In: Proc. 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2002), Dubrovnik, Croatia, September 2002, pp. 1099–1102 (2002)Google Scholar
  16. 16.
    Vogt, J., Koora, K., Finger, A., Fettweis, G.: Comparison of Different Turbo Decoder Realizations for IMT-2000. In: Proc. 1999 GlobalTelecommunications Conference (Globecom 1999), Rio de Janeiro, Brazil, December 1999, vol. 5, pp. 2704–2708 (1999)Google Scholar
  17. 17.
    Worm, A.: Implementation Issues of Turbo-Decoders. PhD thesis, Institute of Microelectronic Systems, Department of Electrical Engineering and Information Technology, University of Kaiserslautern (2001) ISBN 3-925178-72-4Google Scholar
  18. 18.
    Worm, A., Michel, H., Wehn, N.: Power minimization by optimizing data transfers in Turbo-decoders. In: Kleinheubacher Berichte, vol 43, pp. 343–350 (September 1999)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Frank Gilbert
    • 1
  • Norbert Wehn
    • 1
  1. 1.Microelectronic System Design Research GroupUniversity of KaiserslauternKaiserslauternGermany

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