Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders

  • Frank Gilbert
  • Norbert Wehn
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)


The outstanding forward error correction provided by Turbo-Codes made them part of today’s communications standards. Therefore, efficient Turbo-Decoder architectures are important building blocks in communications systems. In this paper we present a scalable, highly parallel architecture for UMTS compliant Turbo decoding and apply architecture-driven voltage scaling to reduce the energy consumption. We will show that this approach adds some additional, more energy-efficient solutions to the design space of Turbo decoding systems. It can save up to 34 % of the decoding energy per datablock, although the supply voltage can not arbitrarily selected. We present throughput, area, and estimated energy results for various degrees of parallelization based on synthesis on a 0.18 μm ASIC-technology library, which is characterized for two different supply voltages: nominal 1.8 V and nominal 1.3 V.


Supply Voltage Signal Processing System Turbo Decode Versus Supply Voltage Important Building Block 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Frank Gilbert
    • 1
  • Norbert Wehn
    • 1
  1. 1.Microelectronic System Design Research GroupUniversity of KaiserslauternKaiserslauternGermany

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